| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 2 | -3/+14 |
| * | No limit for length of lines in BLIF front-end | Clifford Wolf | 2016-10-19 | 1 | -1/+7 |
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 3 | -5/+5 |
| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 3 | -5/+19 |
| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -4/+8 |
| * | Added liberty parser support for types within cell decls | Clifford Wolf | 2016-09-23 | 1 | -39/+46 |
| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 2 | -2/+141 |
| * | Added support for bus interfaces to "read_liberty -lib" | Clifford Wolf | 2016-09-18 | 1 | -1/+77 |
| * | Added assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+1 |
| * | Bugfix in parsing of BLIF latch init values | Clifford Wolf | 2016-09-06 | 1 | -1/+1 |
| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 3 | -1/+13 |
| * | Added $anyconst support to yosys-smtbmc | Clifford Wolf | 2016-08-30 | 1 | -0/+2 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 3 | -6/+6 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 6 | -14/+3 |
| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 4 | -5/+40 |
| * | Improved verilog parser errors | Clifford Wolf | 2016-08-25 | 1 | -0/+3 |
| * | Added SV "restrict" keyword | Clifford Wolf | 2016-08-24 | 1 | -1/+2 |
| * | Fixed bug with memories that do not have a down-to-zero data width | Clifford Wolf | 2016-08-22 | 1 | -2/+13 |
| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 3 | -7/+31 |
| * | Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() | Clifford Wolf | 2016-08-21 | 1 | -4/+15 |
| * | Fixed finish_addr handling in $readmemh/$readmemb | Clifford Wolf | 2016-08-20 | 1 | -3/+3 |
| * | Optimize memory address port width in wreduce and memory_collect, not verilog... | Clifford Wolf | 2016-08-19 | 2 | -4/+13 |
| * | Only allow posedge/negedge with 1 bit wide signals | Clifford Wolf | 2016-08-10 | 1 | -0/+2 |
| * | Fixed bug in parsing real constants | Clifford Wolf | 2016-08-06 | 1 | -4/+4 |
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 3 | -1/+50 |
| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 3 | -9/+30 |
| * | Fixed a verilog parser memory leak | Clifford Wolf | 2016-07-25 | 1 | -0/+1 |
| * | Fixed parsing of empty positional cell ports | Clifford Wolf | 2016-07-25 | 1 | -2/+31 |
| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 3 | -8/+11 |
| * | Using $initstate in "initial assume" and "initial assert" | Clifford Wolf | 2016-07-21 | 1 | -1/+6 |
| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 2 | -0/+26 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 6 | -12/+16 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 6 | -8/+25 |
| * | Fixed mem assignment in left-hand-side concatenation | Clifford Wolf | 2016-07-08 | 1 | -0/+44 |
| * | Allow defining input ports as "input logic" in SystemVerilog | Ruben Undheim | 2016-06-20 | 1 | -2/+2 |
| * | Merge branch 'sv_packages' of https://github.com/rubund/yosys | Clifford Wolf | 2016-06-19 | 5 | -1/+49 |
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| | * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 1 | -2/+2 |
| | * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 5 | -1/+49 |
| * | | Added "read_blif -sop" | Clifford Wolf | 2016-06-18 | 1 | -5/+10 |
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| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 2 | -24/+80 |
| * | Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} | Clifford Wolf | 2016-05-27 | 1 | -0/+11 |
| * | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 2 | -6/+23 |
| * | fixed typos in error messages | Clifford Wolf | 2016-05-27 | 1 | -3/+3 |
| * | Small improvements in Verilog front-end docs | Clifford Wolf | 2016-05-20 | 1 | -0/+3 |
| * | Include <cmath> in yosys.h | Clifford Wolf | 2016-05-08 | 1 | -9/+0 |
| * | Added support for "active high" and "active low" latches in BLIF front-end | Clifford Wolf | 2016-04-22 | 1 | -0/+4 |
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 7 | -8/+8 |
| * | Fixed handling of parameters and const functions in casex/casez pattern | Clifford Wolf | 2016-04-21 | 5 | -8/+37 |
| * | Do not set "nosync" on task outputs, fixes #134 | Clifford Wolf | 2016-03-24 | 1 | -1/+2 |
| * | Added support for $stop system task | Clifford Wolf | 2016-03-21 | 1 | -5/+5 |
