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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-19 18:38:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-19 18:38:25 +0200 |
| commit | f6629b9c29838879cec6a94d6cb47afc6fbd2db4 (patch) | |
| tree | a75ca899efb7a6d8889fada7a35e298521174457 /frontends | |
| parent | 9b8e06bee177f53c34a9dd6dd907a822f21659be (diff) | |
| download | yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.tar.gz yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.tar.bz2 yosys-f6629b9c29838879cec6a94d6cb47afc6fbd2db4.zip | |
Optimize memory address port width in wreduce and memory_collect, not verilog front-end
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 12 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 5 |
2 files changed, 13 insertions, 4 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index bee2256e3..115f8d122 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1253,13 +1253,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); + RTLIL::SigSpec addr_sig = children[0]->genRTLIL(); + cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1)); - cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits)); + cell->setPort("\\ADDR", addr_sig); cell->setPort("\\DATA", RTLIL::SigSpec(wire)); cell->parameters["\\MEMID"] = RTLIL::Const(str); - cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits); + cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width); cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); @@ -1290,11 +1292,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->parameters["\\WORDS"] = RTLIL::Const(num_words); } - cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits)); + SigSpec addr_sig = children[0]->genRTLIL(); + + cell->setPort("\\ADDR", addr_sig); cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words)); cell->parameters["\\MEMID"] = RTLIL::Const(str); - cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits); + cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width); if (type == AST_MEMWR) { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 79dc3b7c8..6ff117a44 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1490,6 +1490,11 @@ skip_dynamic_range_lvalue_expansion:; int mem_width, mem_size, addr_bits; children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); + int addr_width_hint = -1; + bool addr_sign_hint = true; + children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint); + addr_bits = std::max(addr_bits, addr_width_hint); + AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true))); wire_addr->str = id_addr; current_ast_mod->children.push_back(wire_addr); |