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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-25 11:44:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-25 11:44:37 +0200 |
| commit | 4be4969bae5d99af572ca99859dc4a550c24d4cf (patch) | |
| tree | d794e254d5a9a4a56f4f1069c9f12edbd8eeae97 /frontends | |
| parent | ad56ad44c3bdd3d075a32879785a04e3e30491eb (diff) | |
| download | yosys-4be4969bae5d99af572ca99859dc4a550c24d4cf.tar.gz yosys-4be4969bae5d99af572ca99859dc4a550c24d4cf.tar.bz2 yosys-4be4969bae5d99af572ca99859dc4a550c24d4cf.zip | |
Improved verilog parser errors
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 7b025db23..d0d6a5fe1 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -135,6 +135,9 @@ static void free_attr(std::map<std::string, AstNode*> *al) %left OP_POW %right UNARY_OPS +%define parse.error verbose +%define parse.lac full + %expect 2 %debug |