Added "yosys -D" feature

7 files changed, 8 insertions, 8 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index c49f29ce7..64fd0a49c 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1042,7 +1042,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 	if (stripped_name.substr(0, 9) == "$abstract")
 		stripped_name = stripped_name.substr(9);
 
-	log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
+	log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
 
 	current_ast = NULL;
 	flag_dump_ast1 = false;
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index ee0e771e9..a028c4336 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -399,7 +399,7 @@ struct BlifFrontend : public Frontend {
 	}
 	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing BLIF frontend.\n");
+		log_header(design, "Executing BLIF frontend.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc
index 7361a254b..ed6789987 100644
--- a/frontends/ilang/ilang_frontend.cc
+++ b/frontends/ilang/ilang_frontend.cc
@@ -47,7 +47,7 @@ struct IlangFrontend : public Frontend {
 	}
 	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ILANG frontend.\n");
+		log_header(design, "Executing ILANG frontend.\n");
 		extra_args(f, filename, args, 1);
 		log("Input filename: %s\n", filename.c_str());
 
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index f02a73230..0be58b6da 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -437,7 +437,7 @@ struct LibertyFrontend : public Frontend {
 		bool flag_ignore_miss_dir  = false;
 		std::vector<std::string> attributes;
 
-		log_header("Executing Liberty frontend.\n");
+		log_header(design, "Executing Liberty frontend.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b0fdedccd..7dd36a747 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -850,7 +850,7 @@ struct VerificPass : public Pass {
 #ifdef YOSYS_ENABLE_VERIFIC
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
+		log_header(design, "Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
 
 		Message::SetConsoleOutput(0);
 		Message::RegisterCallBackMsg(msg_func);
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 11c2824c3..f8ccda181 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -186,7 +186,7 @@ struct VerilogFrontend : public Frontend {
 		formal_mode = false;
 		default_nettype_wire = true;
 
-		log_header("Executing Verilog-2005 frontend.\n");
+		log_header(design, "Executing Verilog-2005 frontend.\n");
 
 		args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
 
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc
index 80bf243f0..6f9c0e3f5 100644
--- a/frontends/vhdl2verilog/vhdl2verilog.cc
+++ b/frontends/vhdl2verilog/vhdl2verilog.cc
@@ -74,7 +74,7 @@ struct Vhdl2verilogPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n");
+		log_header(design, "Executing VHDL2VERILOG (importing VHDL designs using vhdl2verilog).\n");
 		log_push();
 
 		std::string out_file, top_entity;
@@ -173,7 +173,7 @@ struct Vhdl2verilogPass : public Pass {
 			Frontend::frontend_call(design, &ff, stringf("%s/vhdl2verilog_output.v", tempdir_name.c_str()), "verilog");
 		}
 
-		log_header("Removing temp directory `%s':\n", tempdir_name.c_str());
+		log_header(design, "Removing temp directory `%s':\n", tempdir_name.c_str());
 		remove_directory(tempdir_name);
 		log_pop();
 	}