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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-22 14:27:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-22 14:27:46 +0200 |
| commit | 450f6f59b494af14014f0cbe93df4ceca0eecd76 (patch) | |
| tree | 783ba57115992f646da109c722237060d8033689 /frontends | |
| parent | cad40fc87449e69a086a627bfb25aa49ae400753 (diff) | |
| download | yosys-450f6f59b494af14014f0cbe93df4ceca0eecd76.tar.gz yosys-450f6f59b494af14014f0cbe93df4ceca0eecd76.tar.bz2 yosys-450f6f59b494af14014f0cbe93df4ceca0eecd76.zip | |
Fixed bug with memories that do not have a down-to-zero data width
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/simplify.cc | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index c957389c3..a8fea8211 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -883,11 +883,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); + int data_range_left = id2ast->children[0]->range_left; + int data_range_right = id2ast->children[0]->range_right; + std::stringstream sstr; - sstr << "$mem2bits$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++); + sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++); std::string wire_id = sstr.str(); - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); + AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); wire->str = wire_id; if (current_block) wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); @@ -1491,6 +1494,10 @@ skip_dynamic_range_lvalue_expansion:; int mem_width, mem_size, addr_bits; children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits); + int data_range_left = children[0]->id2ast->children[0]->range_left; + int data_range_right = children[0]->id2ast->children[0]->range_right; + int mem_data_range_offset = std::min(data_range_left, data_range_right); + int addr_width_hint = -1; bool addr_sign_hint = true; children[0]->children[0]->children[0]->detectSignWidthWorker(addr_width_hint, addr_sign_hint); @@ -1553,6 +1560,7 @@ skip_dynamic_range_lvalue_expansion:; { int offset = children[0]->children[1]->range_right; int width = children[0]->children[1]->range_left - offset + 1; + offset -= mem_data_range_offset; std::vector<RTLIL::State> padding_x(offset, RTLIL::State::Sx); @@ -1574,6 +1582,9 @@ skip_dynamic_range_lvalue_expansion:; AstNode *right_at_zero_ast = the_range->children.size() >= 2 ? the_range->children[1]->clone() : left_at_zero_ast->clone(); AstNode *offset_ast = right_at_zero_ast->clone(); + if (mem_data_range_offset) + offset_ast = new AstNode(AST_SUB, offset_ast, mkconst_int(mem_data_range_offset, true)); + while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) |