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authorClifford Wolf <clifford@clifford.at>2016-05-20 16:21:35 +0200
committerClifford Wolf <clifford@clifford.at>2016-05-20 16:21:35 +0200
commit060bf4819a3742ba2ad8142c9a7e665555c22ac7 (patch)
treece4033c346738807072ea2d5fad9ff9490aab490 /frontends
parentffcdc53a18197e40571b9c604fff07408cc12346 (diff)
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Small improvements in Verilog front-end docs
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verilog/verilog_frontend.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index f8ccda181..576f068b3 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -159,6 +159,9 @@ struct VerilogFrontend : public Frontend {
log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
log("the syntax of the code, rather than to rely on read_verilog for that.\n");
log("\n");
+ log("See the Yosys README file for a list of non-standard Verilog features\n");
+ log("supported by the Yosys Verilog front-end.\n");
+ log("\n");
}
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{