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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-10 19:32:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-10 19:32:11 +0200 |
| commit | e9fe57c75e225f80156ceabbc10741c3cfee1c87 (patch) | |
| tree | 9cc93d6263138c30184cb4b97b23dcae751922dd /frontends | |
| parent | 73b7232ec89d9e3611ee5dbbc0cf663a33b09c8f (diff) | |
| download | yosys-e9fe57c75e225f80156ceabbc10741c3cfee1c87.tar.gz yosys-e9fe57c75e225f80156ceabbc10741c3cfee1c87.tar.bz2 yosys-e9fe57c75e225f80156ceabbc10741c3cfee1c87.zip | |
Only allow posedge/negedge with 1 bit wide signals
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 04cdb9416..bee2256e3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -241,6 +241,8 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::SyncRule *syncrule = new RTLIL::SyncRule; syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn; syncrule->signal = child->children[0]->genRTLIL(); + if (GetSize(syncrule->signal) != 1) + log_error("Found posedge/negedge event on a signal that is not 1 bit wide at %s:%d!\n", always->filename.c_str(), always->linenum); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); proc->syncs.push_back(syncrule); } |