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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-27 17:55:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-27 17:55:03 +0200 |
| commit | 766032c5f85e33c8aabb69d1868c3493f254695f (patch) | |
| tree | d8ba9741cbd41716e27a6b939673afa103ecc31c /frontends | |
| parent | ee071586c55915c6535bad0a47bf80c8f2029272 (diff) | |
| download | yosys-766032c5f85e33c8aabb69d1868c3493f254695f.tar.gz yosys-766032c5f85e33c8aabb69d1868c3493f254695f.tar.bz2 yosys-766032c5f85e33c8aabb69d1868c3493f254695f.zip | |
Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index e5446dae6..0e5029eb4 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -429,6 +429,17 @@ struct AST_INTERNAL::ProcessGenerator { RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue; RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap()); + + pool<SigBit> lvalue_sigbits; + for (int i = 0; i < GetSize(lvalue); i++) { + if (lvalue_sigbits.count(lvalue[i]) > 0) { + unmapped_lvalue.remove(i); + lvalue.remove(i); + rvalue.remove(i--); + } else + lvalue_sigbits.insert(lvalue[i]); + } + lvalue.replace(subst_lvalue_map.stdmap()); if (ast->type == AST_ASSIGN_EQ) { |