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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-30 19:27:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-30 19:27:42 +0200 |
| commit | aa25a4cec66bfde84f9142b21679e82ba90ee910 (patch) | |
| tree | d409ee17068e6e41c2049b1b3339d2f49972b9f5 /frontends | |
| parent | 6f41e5277d1d41db7a620c73cf1b65558b55f236 (diff) | |
| download | yosys-aa25a4cec66bfde84f9142b21679e82ba90ee910.tar.gz yosys-aa25a4cec66bfde84f9142b21679e82ba90ee910.tar.bz2 yosys-aa25a4cec66bfde84f9142b21679e82ba90ee910.zip | |
Added $anyconst support to yosys-smtbmc
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 569d2b6ab..03596411f 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1468,9 +1468,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); Cell *cell = current_module->addCell(myid, str.substr(1)); + cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); cell->parameters["\\WIDTH"] = width; Wire *wire = current_module->addWire(myid + "_wire", width); + wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); cell->setPort("\\Y", wire); is_signed = sign_hint; |