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| author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
| commit | bdc316db50cd8b68ef096386a89c1b38793784e1 (patch) | |
| tree | 507341053afa28df1a753ef9de33c3d096683720 /frontends | |
| parent | 2733994aeba0879533cc1a871aae84497b32ff9e (diff) | |
| download | yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.gz yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.bz2 yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.zip | |
Added $anyseq cell type
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 4 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 229a3b596..7c661e8f3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -762,7 +762,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_FCALL: - if (str == "\\$anyconst") { + if (str == "\\$anyconst" || str == "\\$anyseq") { if (GetSize(children) == 1) { while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) @@ -1465,7 +1465,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } break; case AST_FCALL: { - if (str == "\\$anyconst") + if (str == "\\$anyconst" || str == "\\$anyseq") { string myid = stringf("%s$%d", str.c_str() + 1, autoidx++); int width = width_hint; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 57aa648ce..d58b1c283 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1807,8 +1807,8 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - // $anyconst is mapped in AstNode::genRTLIL() - if (str == "\\$anyconst") { + // $anyconst and $anyseq are mapped in AstNode::genRTLIL() + if (str == "\\$anyconst" || str == "\\$anyseq") { recursion_counter--; return false; } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index c730ce5b2..5bbda5355 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1229,7 +1229,7 @@ rvalue: $$ = new AstNode(AST_IDENTIFIER, $2); $$->str = *$1; delete $1; - if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst")) + if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$anyseq")) $$->type = AST_FCALL; } | hierarchical_id non_opt_multirange { |