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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:41:22 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-27 15:41:22 +0200 |
| commit | 40563129872f5a2287f54cb0dbd79534b493a5d6 (patch) | |
| tree | 0ef8462549bafba7356efd94570a19d230b68af9 /frontends | |
| parent | a7b07696238dbfd8e4fb5fd41d597200abef4909 (diff) | |
| download | yosys-40563129872f5a2287f54cb0dbd79534b493a5d6.tar.gz yosys-40563129872f5a2287f54cb0dbd79534b493a5d6.tar.bz2 yosys-40563129872f5a2287f54cb0dbd79534b493a5d6.zip | |
Added $anyconst and $aconst
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 45 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 4 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
3 files changed, 50 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 2fb95ff5a..04cdb9416 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -750,6 +750,19 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun width_hint = max(width_hint, this_width); break; + case AST_FCALL: + if (str == "\\$anyconst" || str == "\\$aconst") { + if (GetSize(children) == 1) { + while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } + if (children[0]->type != AST_CONSTANT) + log_error("System function %s called with non-const argument at %s:%d!\n", + RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + width_hint = max(width_hint, int(children[0]->asInt(true))); + } + break; + } + /* fall through */ + // everything should have been handled above -> print error if not. default: for (auto f : log_files) @@ -1427,6 +1440,38 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) delete always; } break; + case AST_FCALL: { + if (str == "\\$anyconst" || str == "\\$aconst") + { + string myid = stringf("%s$%d", RTLIL::unescape_id(str).c_str(), autoidx++); + int width = width_hint; + + if (GetSize(children) > 1) + log_error("System function %s got %d arguments, expected 1 or 0 at %s:%d.\n", + RTLIL::unescape_id(str).c_str(), GetSize(children), filename.c_str(), linenum); + + if (GetSize(children) == 1) { + if (children[0]->type != AST_CONSTANT) + log_error("System function %s called with non-const argument at %s:%d!\n", + RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + width = children[0]->asInt(true); + } + + if (width <= 0) + log_error("Failed to detect width of %s at %s:%d!\n", + RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum); + + Cell *cell = current_module->addCell(myid, str.substr(1)); + cell->parameters["\\WIDTH"] = width; + + Wire *wire = current_module->addWire(myid + "_wire", width); + cell->setPort("\\Y", wire); + + is_signed = sign_hint; + return SigSpec(wire); + } + } /* fall through */ + // everything should have been handled above -> print error if not. default: for (auto f : log_files) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9f88cddc2..79dc3b7c8 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1655,6 +1655,10 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } + // $anyconst and $aconst are mapped in AstNode::genRTLIL() + if (str == "\\$anyconst" || str == "\\$aconst") + return false; + if (str == "\\$clog2") { if (children.size() != 1) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4cb65a088..c2327011f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1219,7 +1219,7 @@ rvalue: $$ = new AstNode(AST_IDENTIFIER, $2); $$->str = *$1; delete $1; - if ($2 == nullptr && $$->str == "\\$initstate") + if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$aconst")) $$->type = AST_FCALL; } | hierarchical_id non_opt_multirange { |