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* Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-18136-896/+2726
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| * Merge pull request #1421 from YosysHQ/eddie/pr1352Miodrag Milanović2019-10-1833-0/+669
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| | * Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-18119-987/+2470
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| * | Merge pull request #1420 from YosysHQ/eddie/pr1363Miodrag Milanović2019-10-1829-47/+544
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| | * | hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
| | * | Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
| | * | remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
| | * | remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
| | * | split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
| | * | Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
| | * | Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
| | * | Fix formattingMiodrag Milanovic2019-10-171-1/+8
| | * | Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
| | * | Removed alu and div_mod test as agreed, ignore generated filesMiodrag Milanovic2019-10-175-70/+1
| | * | Test per flip-flop typeMiodrag Milanovic2019-10-172-47/+37
| | * | Add -assertEddie Hung2019-10-171-1/+1
| | * | Use built-in async2sync call as per #1417Eddie Hung2019-10-171-4/+0
| | * | Update mul test to DSP48E1Eddie Hung2019-10-171-9/+2
| | * | Update area for div_modEddie Hung2019-10-171-6/+6
| | * | Add comment for lack of tristate logic pointing to #1225Eddie Hung2019-10-171-1/+1
| | * | Move $x to end as 7f0eec8Eddie Hung2019-10-171-1/+1
| | * | adffs test update (equiv_opt -multiclock)SergeyDegtyar2019-10-171-5/+6
| | * | Fix div_mod testSergey2019-10-171-1/+1
| | * | Fix div_mod testSergey2019-10-171-1/+1
| | * | Fix div_mod testSergey2019-10-171-1/+1
| | * | Fix div_mod testSergey2019-10-171-1/+1
| | * | Fix div_mod testSergey2019-10-171-1/+1
| | * | Fix div_mod testSergey2019-10-171-1/+1
| | * | Add comment with expected behavior for latches,tribuf tests;Update adffs testSergeyDegtyar2019-10-174-14/+11
| | * | Fix latches.ys testSergeyDegtyar2019-10-171-4/+3
| | * | Remove xilinx_ug901 tests (will be moved to yosys-tests)SergeyDegtyar2019-10-1789-2963/+0
| | * | Add smoke tests to tests/xilinxSergeyDegtyar2019-10-1730-9/+655
| | * | Add comments for unproven cells.SergeyDegtyar2019-10-173-2/+3
| | * | Add tests for Xilinx UG901 examplesSergeyDegtyar2019-10-1789-0/+2962
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| * | Merge pull request #1450 from YosysHQ/clifford/fixdffmuxClifford Wolf2019-10-165-155/+270
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| | * | Fix dffmux peepopt init handlingClifford Wolf2019-10-162-27/+113
| | * | Move GENERATE_PATTERN macro to separate utility headerClifford Wolf2019-10-163-128/+157
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| * | Disable left-over log_debug in peepopt_dffmux.pmgClifford Wolf2019-10-161-1/+1
| * | Fix parsing of .cname BLIF statementsClifford Wolf2019-10-161-1/+1
| * | Add .blackbox support to blif front-endClifford Wolf2019-10-161-0/+6
| * | Merge pull request #1448 from YosysHQ/daveshah1-sv-experimentsClifford Wolf2019-10-1417-20/+315
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| | * \ Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-1417-20/+315
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| | | * | frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | * | sv: Improve testsDavid Shah2019-10-038-7/+30
| | | * | sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | * | sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | * | Update CHANGELOG and READMEDavid Shah2019-10-032-0/+3
| | | * | sv: Add test scripts for typedefsDavid Shah2019-10-035-0/+31
| | | * | sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | * | sv: Add %expectDavid Shah2019-10-031-0/+1
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