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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-11 17:01:19 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a (patch) | |
| tree | 7972341001cc4577926ef0590278f024c35edbf9 | |
| parent | 489444bcba0d54a45605872eb466792f07357f84 (diff) | |
| download | yosys-7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a.tar.gz yosys-7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a.tar.bz2 yosys-7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a.zip | |
Add comment with expected behavior for latches,tribuf tests;Update adffs test
| -rw-r--r-- | tests/xilinx/adffs.v | 18 | ||||
| -rw-r--r-- | tests/xilinx/adffs.ys | 5 | ||||
| -rw-r--r-- | tests/xilinx/latches.ys | 1 | ||||
| -rw-r--r-- | tests/xilinx/tribuf.ys | 1 |
4 files changed, 11 insertions, 14 deletions
diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 96d8e176f..38c82a36f 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 3 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 4 t:LUT2 -select -assert-count 4 t:LUT3 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D +select -assert-count 5 t:LUT2 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 042ee2d4f..1f643cb4e 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -15,5 +15,6 @@ flatten cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 +#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. select -assert-count 3 t:$_DLATCH_P_ select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index fc7ed37ef..76b00647d 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,5 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D |