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* simul: fix resolved associationTristan Gingold2022-09-172-2/+3
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-172-5/+4
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-172-2/+2
* synth: handle protected types in subprogramsTristan Gingold2022-09-171-31/+3
* synth: preliminary work to factorize codeTristan Gingold2022-09-161-13/+5
* simul: handle active attributeTristan Gingold2022-09-161-10/+49
* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
* simul: improve error handling during elaborationTristan Gingold2022-09-161-0/+1
* simul: handle more signals typesTristan Gingold2022-09-152-23/+128
* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-121-0/+1
* simul: move assertions (not to trigger in case of errors)Tristan Gingold2022-09-111-3/+3
* simul: optimize resolution call only for std_logicTristan Gingold2022-09-111-5/+11
* synth: fix and add checks for memory management.Tristan Gingold2022-09-101-6/+17
* simul: add support for protected objectsTristan Gingold2022-09-082-2/+62
* elab-vhdl_values: factorize codeTristan Gingold2022-09-071-2/+2
* simul: do not propagate errors from resolution functionTristan Gingold2022-09-071-0/+3
* simul: fix computation for number of driversTristan Gingold2022-09-061-1/+2
* synth: handle generics in blocksTristan Gingold2022-09-062-3/+21
* simul: add an hook to display report/assert messageTristan Gingold2022-09-061-14/+50
* synth: use areapoolsTristan Gingold2022-09-023-90/+139
* synth: factorize code for tracing statements executionTristan Gingold2022-09-021-3/+7
* simul: detect multiple drivers for unresolved signalsTristan Gingold2022-09-021-8/+93
* simul-vhdl_simul: simplify procedure connectTristan Gingold2022-08-261-41/+22
* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-251-1/+2
* simul: improve support of float signalsTristan Gingold2022-08-241-3/+7
* simul: handle conversions and associations with constantsTristan Gingold2022-08-242-70/+399
* simul: simplify codeTristan Gingold2022-08-231-16/+4
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-234-120/+50
* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-233-14/+152
* simul-vhdl_simul: handle waveforms in signal assignmentsTristan Gingold2022-08-211-40/+47
* simul: rework assertions execution and error handlingTristan Gingold2022-08-211-3/+4
* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
* simul: handle after clauses in signal assignmentTristan Gingold2022-08-211-70/+93
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-202-14/+267
* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-192-43/+297
* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-182-3/+4
* simul: handle individual associationsTristan Gingold2022-08-172-4/+16
* simul: add create_connectsTristan Gingold2022-08-174-46/+144
* simul: create terminals (WIP)Tristan Gingold2022-08-174-8/+62
* simul-vhdl_simul: add scalar terminal tableTristan Gingold2022-07-281-0/+16
* simul-vhdl_debug: add info terminalTristan Gingold2022-07-281-20/+69
* simul: gather terminalsTristan Gingold2022-07-252-0/+43
* src/simul: rewrite of ghdl/simul based on synthTristan Gingold2022-07-247-0/+3759
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