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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-23 07:37:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-23 07:37:03 +0200 |
| commit | 9d3256ce533eead5b554e7e59a07d5451d964a4c (patch) | |
| tree | 9b78d9d0027b8e181a34c334079d8f7016df3561 /src/simul | |
| parent | 6961b3f82d0be3d891805ac32f8028cc15b3aa4e (diff) | |
| download | ghdl-9d3256ce533eead5b554e7e59a07d5451d964a4c.tar.gz ghdl-9d3256ce533eead5b554e7e59a07d5451d964a4c.tar.bz2 ghdl-9d3256ce533eead5b554e7e59a07d5451d964a4c.zip | |
simul: simplify code
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 20 |
1 files changed, 4 insertions, 16 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 70305d04f..e37c4aa7e 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -246,22 +246,10 @@ package body Simul.Vhdl_Simul is begin case Typ.Kind is when Type_Logic - | Type_Bit => - Grt.Signals.Ghdl_Signal_Add_Port_Driver_E8 - (Read_Sig (Sig), Read_U8 (Val)); - when Type_Discrete => - if Typ.Sz = 1 then - Grt.Signals.Ghdl_Signal_Add_Port_Driver_E8 - (Read_Sig (Sig), Read_U8 (Val)); - elsif Typ.Sz = 4 then - Grt.Signals.Ghdl_Signal_Add_Port_Driver_I32 - (Read_Sig (Sig), Read_I32 (Val)); - elsif Typ.Sz = 8 then - Grt.Signals.Ghdl_Signal_Add_Port_Driver_I64 - (Read_Sig (Sig), Read_I64 (Val)); - else - raise Internal_Error; - end if; + | Type_Bit + | Type_Discrete => + Grt.Signals.Ghdl_Process_Add_Port_Driver + (Read_Sig (Sig), To_Ghdl_Value ((Typ, Val))); when Type_Vector | Type_Array => declare |