diff options
| author | Tristan Gingold <tgingold@free.fr> | 2022-08-24 21:53:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-24 21:53:04 +0200 |
| commit | 1ac09fc1b9344b41054f1f86263f768e526a6e7f (patch) | |
| tree | 7e3f04f767da182d7f9491a0f2d1f76f0de57a6a /src/simul | |
| parent | 461261a43ef650a42d8a39018acbbd6a2cdff8a6 (diff) | |
| download | ghdl-1ac09fc1b9344b41054f1f86263f768e526a6e7f.tar.gz ghdl-1ac09fc1b9344b41054f1f86263f768e526a6e7f.tar.bz2 ghdl-1ac09fc1b9344b41054f1f86263f768e526a6e7f.zip | |
simul: improve support of float signals
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index f18943770..fbd649142 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -185,6 +185,8 @@ package body Simul.Vhdl_Simul is else raise Internal_Error; end if; + when Type_Float => + Val.F64 := Ghdl_F64 (Read_Fp64 (Mt.Mem)); when others => raise Internal_Error; end case; @@ -269,11 +271,12 @@ package body Simul.Vhdl_Simul is case Typ.Kind is when Type_Logic | Type_Bit - | Type_Discrete => + | Type_Discrete + | Type_Float => Grt.Signals.Ghdl_Process_Add_Port_Driver (Read_Sig (Sig), To_Ghdl_Value ((Typ, Val))); when Type_Vector - | Type_Array => + | Type_Array => declare Len : constant Uns32 := Typ.Abound.Len; begin @@ -1334,7 +1337,8 @@ package body Simul.Vhdl_Simul is case Typ.Kind is when Type_Logic | Type_Bit - | Type_Discrete => + | Type_Discrete + | Type_Float => Grt.Processes.Ghdl_Process_Add_Sensitivity (Read_Sig (Sig)); when Type_Vector | Type_Array => |