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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-21 10:39:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-21 10:39:12 +0200 |
| commit | 61665a183e94cf8edaebb336c34df24a02ef45fd (patch) | |
| tree | 27a723c64906a5f7293e47e9cb27c62ca3b33574 /src/simul | |
| parent | 068988b5f9132ae11ee65ca75ac6e56bc8f2f530 (diff) | |
| download | ghdl-61665a183e94cf8edaebb336c34df24a02ef45fd.tar.gz ghdl-61665a183e94cf8edaebb336c34df24a02ef45fd.tar.bz2 ghdl-61665a183e94cf8edaebb336c34df24a02ef45fd.zip | |
simul: rework assertions execution and error handling
Diffstat (limited to 'src/simul')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 63e747e9d..383203e92 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1067,7 +1067,7 @@ package body Simul.Vhdl_Simul is end; when Iir_Kind_Assertion_Statement => - Synth.Vhdl_Stmts.Execute_Assertion_Statement (Inst, Stmt); + Execute_Assertion_Statement (Inst, Stmt); Next_Statement (Process, Stmt); when Iir_Kind_Report_Statement => Synth.Vhdl_Stmts.Execute_Report_Statement (Inst, Stmt); @@ -1275,8 +1275,7 @@ package body Simul.Vhdl_Simul is if Elab.Debugger.Flag_Need_Debug then Elab.Debugger.Debug_Break (Process.Instance, Process.Proc); end if; - Synth.Vhdl_Stmts.Execute_Assertion_Statement - (Process.Instance, Process.Proc); + Execute_Assertion_Statement (Process.Instance, Process.Proc); when Iir_Kind_Concurrent_Simple_Signal_Assignment => if Elab.Debugger.Flag_Need_Debug then Elab.Debugger.Debug_Break (Process.Instance, Process.Proc); @@ -2671,6 +2670,8 @@ package body Simul.Vhdl_Simul is Grt.Options.Progname := To_Ghdl_C_String (Ghdl_Progname'Address); Grt.Errors.Set_Error_Stream (Grt.Stdio.stdout); + Elab.Debugger.Error_Hook := Grt.Errors.Fatal_Error'Access; + -- Grt.Errors.Error_Hook := Debug_Error'Access; if Flag_Debug_Elab then |