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Age
Files
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-12
3
-23
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+136
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Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Eddie Hung
2019-12-09
3
-23
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+136
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unmap $__ICE40_CARRY_WRAPPER in test
Eddie Hung
2019-12-09
1
-1
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+21
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ice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung
2019-12-09
1
-3
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+5
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Drop keep=0 attributes on SB_CARRY
Eddie Hung
2019-12-06
1
-2
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+2
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Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
Eddie Hung
2019-12-05
1
-0
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+30
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Check SB_CARRY name also preserved
Eddie Hung
2019-12-03
1
-0
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+1
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Add testcase
Eddie Hung
2019-12-03
1
-0
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+60
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-12-06
6
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+412
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tests: arch: xilinx: Change order of arguments in macc.sh
Jan Kowalewski
2019-12-06
1
-1
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+1
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iopadmap: Refactor and fix tristate buffer mapping. (#1527)
Marcin Kościelnicki
2019-12-04
1
-0
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+99
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Merge pull request #1524 from pepijndevos/gowindffinit
Clifford Wolf
2019-12-03
3
-2
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+301
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update test
Pepijn de Vos
2019-12-03
1
-2
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+3
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Use -match-init to not synth contradicting init values
Pepijn de Vos
2019-12-03
1
-10
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+12
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attempt to fix formatting
Pepijn de Vos
2019-11-25
1
-138
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+138
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gowin: add and test dff init values
Pepijn de Vos
2019-11-25
2
-0
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+296
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abc9: Fix breaking of SCCs
David Shah
2019-12-01
1
-0
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+6
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abc9_map.v to transform INIT=1 to INIT=0
Eddie Hung
2019-12-04
1
-0
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+91
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-0
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+31
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Add multiple driver testcase
Eddie Hung
2019-11-27
1
-0
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+31
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-27
2
-0
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+82
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Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
Eddie Hung
2019-11-27
1
-0
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+69
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No need for -abc9
Eddie Hung
2019-11-26
1
-1
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+1
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Add citation
Eddie Hung
2019-11-26
1
-0
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+1
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Add testcase derived from fastfir_dynamictaps benchmark
Eddie Hung
2019-11-26
1
-0
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+68
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Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
Clifford Wolf
2019-11-27
1
-0
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+13
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opt_share: Fix handling of fine cells.
Marcin Kościelnicki
2019-11-27
1
-0
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+13
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Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung
2019-11-27
1
-9
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+0
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Remove notes
Eddie Hung
2019-11-26
1
-9
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+0
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-2
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+23
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Revert "submod to bitty rather bussy, for bussy wires used as input and output"
Eddie Hung
2019-11-27
1
-2
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+5
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Fix wire width
Eddie Hung
2019-11-26
1
-2
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+2
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Add testcase where \init is copied
Eddie Hung
2019-11-25
1
-0
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+18
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
5
-13
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+24
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-5
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+16
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xilinx: Use INV instead of LUT1 when applicable
Marcin Kościelnicki
2019-11-25
4
-8
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+8
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Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
Eddie Hung
2019-11-23
3
-11
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+11
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Another sloppy mistake!
Eddie Hung
2019-11-21
1
-1
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+1
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Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
Eddie Hung
2019-11-21
3
-4
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+9
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async2sync -> clk2fflogic
Eddie Hung
2019-11-21
1
-1
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+1
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-3
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+0
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Remove redundant flatten
Eddie Hung
2019-11-22
1
-2
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+0
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Stray dump
Eddie Hung
2019-11-22
1
-1
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+0
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-0
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+28
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Add another test with constant driver
Eddie Hung
2019-11-22
1
-0
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+28
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Add testcase for signal used as part input part output
Eddie Hung
2019-11-22
1
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+5
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-0
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+25
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Cleanup spacing
Eddie Hung
2019-11-22
1
-2
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+1
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Add testcase
Eddie Hung
2019-11-22
1
-0
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+26
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Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
2
-1
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+63
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