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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-09 14:20:35 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-09 14:20:35 -0800 |
| commit | eff858cd33403a13736ac74cce6964648306e594 (patch) | |
| tree | 2a5507b31c6267fc52bdc5f09daeb65add7511e5 /tests | |
| parent | bbdf2452b3bf5bd5d835fc1d6936568cb0a32a1a (diff) | |
| download | yosys-eff858cd33403a13736ac74cce6964648306e594.tar.gz yosys-eff858cd33403a13736ac74cce6964648306e594.tar.bz2 yosys-eff858cd33403a13736ac74cce6964648306e594.zip | |
unmap $__ICE40_CARRY_WRAPPER in test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ice40/ice40_opt.ys | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys index 860e2e211..5186d4800 100644 --- a/tests/arch/ice40/ice40_opt.ys +++ b/tests/arch/ice40/ice40_opt.ys @@ -1,4 +1,24 @@ read_verilog -icells -formal <<EOT +module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3); + parameter LUT = 0; + SB_CARRY carry ( + .I0(A), + .I1(B), + .CI(CI), + .CO(CO) + ); + \$lut #( + .WIDTH(4), + .LUT(LUT) + ) lut ( + .A({I0,A,B,I3}), + .Y(O) + ); +endmodule +EOT +design -stash unmap + +read_verilog -icells -formal <<EOT module top(input CI, I0, output [1:0] CO, output O); wire A = 1'b0, B = 1'b0; \$__ICE40_CARRY_WRAPPER #( @@ -20,7 +40,7 @@ module top(input CI, I0, output [1:0] CO, output O); endmodule EOT -equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt +equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt design -load postopt select -assert-count 1 t:* select -assert-count 1 t:$lut |