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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 13:22:26 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 13:22:26 -0800 |
| commit | ff1e35768224a7824ec9838ca84d27bbb4a14676 (patch) | |
| tree | 0ba73a035c00a9c425c0b92bdac80771f70a3bd3 /tests | |
| parent | 1c0ee4f786a77d8557c9dd462abc54982b7b639d (diff) | |
| download | yosys-ff1e35768224a7824ec9838ca84d27bbb4a14676.tar.gz yosys-ff1e35768224a7824ec9838ca84d27bbb4a14676.tar.bz2 yosys-ff1e35768224a7824ec9838ca84d27bbb4a14676.zip | |
Add multiple driver testcase
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/submod.ys | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 552fd4e01..9d7dabdd7 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -15,6 +15,7 @@ proc design -save gold submod +check -assert design -stash gate design -import gold -as gold @@ -41,6 +42,7 @@ proc design -save gold submod +check -assert top design -stash gate design -import gold -as gold @@ -51,6 +53,35 @@ sat -verify -prove-asserts -show-ports miter design -reset +read_verilog <<EOT +module top(input a, output [1:0] b, c); +(* submod="bar" *) sub s1(a, b[0]); +(* submod="bar" *) sub s2(a, c[1]); +assign c = b; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + + +design -reset read_verilog -icells <<EOT module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); |