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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 23:38:49 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 23:38:49 -0800 |
| commit | 6318e3ce6df2484c4cc17856608e2a6354cd643a (patch) | |
| tree | 4fc1d5c29672ab541e91aa766abc8ff5db5cd072 /tests | |
| parent | 5e487b103c3c1ed9f1fcaca21821466628b7ff80 (diff) | |
| download | yosys-6318e3ce6df2484c4cc17856608e2a6354cd643a.tar.gz yosys-6318e3ce6df2484c4cc17856608e2a6354cd643a.tar.bz2 yosys-6318e3ce6df2484c4cc17856608e2a6354cd643a.zip | |
Fix wire width
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/submod.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index f50556d76..a0a3f2da5 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -1,8 +1,8 @@ read_verilog <<EOT -module top(input a, output [1:0] b); +module top(input a, output b); wire c; (* submod="bar" *) sub s1(a, c); -assign b[0] = c; +assign b = c; endmodule module sub(input a, output c); |