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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:03:33 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 01:03:33 -0800 |
| commit | f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26 (patch) | |
| tree | c86d01623e4ac9ebeb91e61441812ddccc20fa07 /tests | |
| parent | 4ba6f4f0d7c5754e04a0347a2b43a8640f7a6a35 (diff) | |
| parent | 5e67df38edf5207a9b816946b094448cd6a52f88 (diff) | |
| download | yosys-f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26.tar.gz yosys-f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26.tar.bz2 yosys-f6c0ec1d09c9bc065cc7266b299b41ebb59d6e26.zip | |
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 99075d319..961e7605e 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -218,12 +218,6 @@ module MUXF8(input I0, I1, S, output O); endmodule // Citation: https://github.com/alexforencich/verilog-ethernet -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q -// returns before b4321a31 -// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no -// driver. -// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no -// driver. module abc9_test022 ( input wire clk, @@ -237,9 +231,6 @@ module abc9_test022 endmodule // Citation: https://github.com/riscv/riscv-bitmanip -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q -// returns before 14233843 -// Warning: Wire abc9_test023.\dout [1] is used but has no driver. module abc9_test023 #( parameter integer N = 2, parameter integer M = 2 |