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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 22:41:35 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 22:41:35 -0800 |
| commit | 15042eaf577eff423924521c1c828584ba66914f (patch) | |
| tree | 8a9cad28de83b056df61a246fd8f465e2f45d93b /tests | |
| parent | a30d5e1cc35791a98b2269c5e587c566fe8b0a35 (diff) | |
| download | yosys-15042eaf577eff423924521c1c828584ba66914f.tar.gz yosys-15042eaf577eff423924521c1c828584ba66914f.tar.bz2 yosys-15042eaf577eff423924521c1c828584ba66914f.zip | |
Remove notes
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 64b625efe..4d5879e6f 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -218,12 +218,6 @@ module MUXF8(input I0, I1, S, output O); endmodule // Citation: https://github.com/alexforencich/verilog-ethernet -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q -// returns before b4321a31 -// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no -// driver. -// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no -// driver. module abc9_test022 ( input wire clk, @@ -237,9 +231,6 @@ module abc9_test022 endmodule // Citation: https://github.com/riscv/riscv-bitmanip -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q -// returns before 14233843 -// Warning: Wire abc9_test023.\dout [1] is used but has no driver. module abc9_test023 #( parameter integer N = 2, parameter integer M = 2 |