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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 22:51:16 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-26 22:51:16 -0800 |
| commit | 4a0198128eb966d00c24bd6938625892e7fd4b95 (patch) | |
| tree | 60b0616f61527daed2e5f1f78ddc91f57bfbb476 /tests | |
| parent | 2105ae176a73a9839670bf8120b462d06151dae5 (diff) | |
| download | yosys-4a0198128eb966d00c24bd6938625892e7fd4b95.tar.gz yosys-4a0198128eb966d00c24bd6938625892e7fd4b95.tar.bz2 yosys-4a0198128eb966d00c24bd6938625892e7fd4b95.zip | |
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Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/dsp_fastfir.ys | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index 30e74a01b..b205d42c1 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -1,4 +1,5 @@ read_verilog <<EOT +// Citation https://github.com/ZipCPU/dspfilters/blob/master/rtl/fastfir.v module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result); wire [30:0] _00_; wire [23:0] _01_; |