diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:50:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:50:56 -0800 |
| commit | 0806b8e398bcf2a6aaaf14c389b2d74c50a9ccab (patch) | |
| tree | da6ed0c7eafae5581f460aeaf82f01c70135dfe7 /tests | |
| parent | 698854955cc3ba3fa575f434c29db9e37dcb09b2 (diff) | |
| parent | 8779faf7891cf1fc394204b12ad1a0e403d22c6b (diff) | |
| download | yosys-0806b8e398bcf2a6aaaf14c389b2d74c50a9ccab.tar.gz yosys-0806b8e398bcf2a6aaaf14c389b2d74c50a9ccab.tar.bz2 yosys-0806b8e398bcf2a6aaaf14c389b2d74c50a9ccab.zip | |
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/submod.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..271a8edef --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module top(input a, output [1:0] b); +wire c; +(* submod="bar" *) sub s1(a, c); +assign b[0] = c; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +flatten +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |