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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 13:24:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 13:24:03 -0800 |
| commit | c61186dd9d802c2e62fb218527b3328ac1754d9d (patch) | |
| tree | ba07f6af78eccf6c95896cbfb0917b79f932fe98 /tests | |
| parent | ac5b5e97bcd56a539a02344584011dd985f13f06 (diff) | |
| parent | 130d3b9639148fa8191937313a3ad21a7827df18 (diff) | |
| download | yosys-c61186dd9d802c2e62fb218527b3328ac1754d9d.tar.gz yosys-c61186dd9d802c2e62fb218527b3328ac1754d9d.tar.bz2 yosys-c61186dd9d802c2e62fb218527b3328ac1754d9d.zip | |
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/submod.ys | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 552fd4e01..9d7dabdd7 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -15,6 +15,7 @@ proc design -save gold submod +check -assert design -stash gate design -import gold -as gold @@ -41,6 +42,7 @@ proc design -save gold submod +check -assert top design -stash gate design -import gold -as gold @@ -51,6 +53,35 @@ sat -verify -prove-asserts -show-ports miter design -reset +read_verilog <<EOT +module top(input a, output [1:0] b, c); +(* submod="bar" *) sub s1(a, b[0]); +(* submod="bar" *) sub s2(a, c[1]); +assign c = b; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + + +design -reset read_verilog -icells <<EOT module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1])); |