iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	verilog: allow spaces in macro arguments	Zachary Snow	2021-01-20	1	-0/+28
*	tests/simple: remove "nullglob" shopt	Xiretza	2020-09-21	1	-1/+0
*	Module name scope support	Zachary Snow	2020-08-20	1	-0/+16
*	Merge pull request #2339 from zachjs/display-format-0s	clairexen	2020-08-18	1	-0/+7
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\| *	Allow %0s $display format specifier	Zachary Snow	2020-08-09	1	-0/+7
* \|	Merge pull request #2338 from zachjs/const-branch-finish	clairexen	2020-08-18	1	-0/+39
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\| * \|	Propagate const_fold through generate blocks and branches	Zachary Snow	2020-08-09	1	-0/+39
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* /	Fix generate scoping issues	Zachary Snow	2020-07-31	1	-0/+85
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*	Expand tests/simple/constmuldivmod.v	Xiretza	2020-05-28	1	-1/+41
*	Bugfix in partsel.v signed indices test cases	Claire Wolf	2020-05-02	1	-2/+2
*	Add tests based on the test case from #1990	Claire Wolf	2020-05-02	1	-0/+46
*	Add dynamic slicing Verilog testcase	Eddie Hung	2020-03-31	1	-0/+12
*	Fix partsel expr bit width handling and add test case	Claire Wolf	2020-03-08	1	-0/+4
*	Make SV2017 compliant courtesy of @wsnyder	Eddie Hung	2019-12-12	1	-3/+1
*	simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select	Eddie Hung	2019-09-05	1	-21/+0
*	Add peepopt_dffmuxext tests	Eddie Hung	2019-09-04	1	-0/+8
*	Use `command -v` rather than `which`	Emily	2019-09-03	1	-1/+1
*	Add test case for real parameters	Clifford Wolf	2019-08-20	1	-1/+10
*	Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...	Jim Lawson	2019-07-31	1	-1/+3
*	Add test	Eddie Hung	2019-06-20	1	-0/+11
*	Add proper test for SV-style arrays	Clifford Wolf	2019-06-20	1	-0/+16
*	Add defvalue test, minor autotest fixes for .sv files	Clifford Wolf	2019-06-19	1	-0/+22
*	Rename implicit_ports.sv test to implicit_ports.v	Clifford Wolf	2019-06-07	1	-0/+0
*	Cleanup tux3-implicit_named_connection	Clifford Wolf	2019-06-07	1	-0/+16
*	Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...	Clifford Wolf	2019-06-07	1	-1/+2
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\| *	SystemVerilog support for implicit named port connections	tux3	2019-06-06	1	-1/+2
* \|	Added tests for attributes	Maciej Kurc	2019-06-03	9	-0/+219
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*	Merge pull request #1049 from YosysHQ/clifford/fix1047	Clifford Wolf	2019-05-28	1	-0/+4
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\| *	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	Clifford Wolf	2019-05-28	1	-0/+4
* \|	Add actual wandwor test that is part of "make test"	Clifford Wolf	2019-05-28	1	-0/+36
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*	Added tests for Verilog frontent for attributes on parameters and localparams	Maciej Kurc	2019-05-16	2	-0/+22
*	Add test case from #997	Clifford Wolf	2019-05-07	1	-0/+12
*	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968	Clifford Wolf	2019-05-06	3	-0/+32
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\| *	Merge pull request #969 from YosysHQ/clifford/pmgenstuff	Clifford Wolf	2019-05-03	1	-0/+9
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\| \| *	Add peepopt_muldiv, fixes #930	Clifford Wolf	2019-04-30	1	-0/+9
\| * \|	Merge pull request #976 from YosysHQ/clifford/fix974	Clifford Wolf	2019-05-03	1	-0/+22
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\| \| * \|	Add splitcmplxassign test case and silence splitcmplxassign warning	Clifford Wolf	2019-05-01	1	-0/+22
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\| * /	Fix #938 - Crash occurs in case when use write_firrtl command	Jim Lawson	2019-05-01	1	-0/+1
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* /	Add additional test cases for for-loops	Clifford Wolf	2019-05-01	1	-0/+25
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*	Add retime test	Eddie Hung	2019-04-05	1	-0/+6
*	fix local name resolution in prefix constructs	Zachary Snow	2019-03-18	1	-0/+56
*	Fix handling of task output ports in clocked always blocks, fixes #857	Clifford Wolf	2019-03-07	1	-0/+19
*	Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails	Jim Lawson	2019-03-04	1	-0/+1
*	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-1/+0
*	Fix handling of defparam for when default_nettype is none	Clifford Wolf	2019-02-24	1	-0/+2
*	Merge https://github.com/YosysHQ/yosys into dff_init	Eddie Hung	2019-02-17	1	-0/+26
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\| *	Update cells supported for verilog to FIRRTL conversion.	Jim Lawson	2019-02-15	1	-0/+26
* \|	Extend testcase	Eddie Hung	2019-02-06	1	-2/+34
* \|	Add testcase	Eddie Hung	2019-02-06	1	-0/+10
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*	Basic test for checking correct synthesis of SystemVerilog interfaces	Ruben Undheim	2018-10-18	1	-90/+0