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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-06 14:02:11 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-06 14:02:11 -0800 |
commit | 03cf1532a70d705ada69dcb8ae79ae405a86b7da (patch) | |
tree | bbb20708f2892944af13838ff4a93bc8d710107c /tests/simple | |
parent | a9674bd2eca5efac6e4f7b2871a01cbba80f64ec (diff) | |
download | yosys-03cf1532a70d705ada69dcb8ae79ae405a86b7da.tar.gz yosys-03cf1532a70d705ada69dcb8ae79ae405a86b7da.tar.bz2 yosys-03cf1532a70d705ada69dcb8ae79ae405a86b7da.zip |
Extend testcase
Diffstat (limited to 'tests/simple')
-rw-r--r-- | tests/simple/dff_init.v | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v index aad378346..be947042e 100644 --- a/tests/simple/dff_init.v +++ b/tests/simple/dff_init.v @@ -1,6 +1,5 @@ -module dff_test(n1, n1_inv, clk); +module dff0_test(n1, n1_inv, clk); input clk; - (* init = 32'd0 *) output n1; reg n1 = 32'd0; output n1_inv; @@ -8,3 +7,36 @@ module dff_test(n1, n1_inv, clk); n1 <= n1_inv; assign n1_inv = ~n1; endmodule + +module dff1_test(n1, n1_inv, clk); + input clk; + (* init = 32'd1 *) + output n1; + reg n1 = 32'd1; + output n1_inv; + always @(posedge clk) + n1 <= n1_inv; + assign n1_inv = ~n1; +endmodule + +module dff0a_test(n1, n1_inv, clk); + input clk; + (* init = 32'd0 *) // Must be consistent with reg initialiser below + output n1; + reg n1 = 32'd0; + output n1_inv; + always @(posedge clk) + n1 <= n1_inv; + assign n1_inv = ~n1; +endmodule + +module dff1a_test(n1, n1_inv, clk); + input clk; + (* init = 32'd1 *) // Must be consistent with reg initialiser below + output n1; + reg n1 = 32'd1; + output n1_inv; + always @(posedge clk) + n1 <= n1_inv; + assign n1_inv = ~n1; +endmodule |