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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-07 19:58:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-07 19:58:04 +0200 |
| commit | b7ec698d4063f0e0ae021050782004c523302b0c (patch) | |
| tree | 290e48c99066bf448cf2f92b6f65f71eb9633e0a /tests/simple | |
| parent | 33738c174560c718723b6c860af002d1a8a91cea (diff) | |
| download | yosys-b7ec698d4063f0e0ae021050782004c523302b0c.tar.gz yosys-b7ec698d4063f0e0ae021050782004c523302b0c.tar.bz2 yosys-b7ec698d4063f0e0ae021050782004c523302b0c.zip | |
Add test case from #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/dff_init.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v index be947042e..375ea5c4d 100644 --- a/tests/simple/dff_init.v +++ b/tests/simple/dff_init.v @@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk); n1 <= n1_inv; assign n1_inv = ~n1; endmodule + +module dff_test_997 (y, clk, wire4); +// https://github.com/YosysHQ/yosys/issues/997 + output wire [1:0] y; + input clk; + input signed wire4; + reg [1:0] reg10 = 0; + always @(posedge clk) begin + reg10 <= wire4; + end + assign y = reg10; +endmodule |