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author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-03-04 13:23:58 -0800 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-03-04 13:37:23 -0800 |
commit | d6c4dfb9020ee19eebe3adadca89b65627184d81 (patch) | |
tree | 51df00d11d4fce0fe2931f65ae857d956e35969c /tests/simple | |
parent | 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 (diff) | |
download | yosys-d6c4dfb9020ee19eebe3adadca89b65627184d81.tar.gz yosys-d6c4dfb9020ee19eebe3adadca89b65627184d81.tar.bz2 yosys-d6c4dfb9020ee19eebe3adadca89b65627184d81.zip |
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".
Diffstat (limited to 'tests/simple')
-rw-r--r-- | tests/simple/xfirrtl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 5bc75347b..50d693513 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,6 +1,7 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of dff_different_styles.v +dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff |