diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:07:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 16:07:22 -0700 |
| commit | c20adc52638b0f3ba3b1c39e5286ae92e901005d (patch) | |
| tree | 4773cd52fecc25644e29438cc6049a856c1ff0ee /tests/simple | |
| parent | c27ab609faeeb3ae9372ea4cf85e5ac6ba029646 (diff) | |
| download | yosys-c20adc52638b0f3ba3b1c39e5286ae92e901005d.tar.gz yosys-c20adc52638b0f3ba3b1c39e5286ae92e901005d.tar.bz2 yosys-c20adc52638b0f3ba3b1c39e5286ae92e901005d.zip | |
Add test
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/generate.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 3c55682cb..0e353ad9b 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -148,3 +148,14 @@ generate endgenerate assign out = steps[WIDTH].outer[0].val; endmodule + +// ------------------------------------------ + +module gen_test6(output [3:0] o); +generate + genvar i; + for (i = 3; i >= 0; i = i-1) begin + assign o[i] = 1'b0; + end +endgenerate +endmodule |