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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-25 16:18:13 -0800 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-02-25 16:18:13 -0800 |
| commit | 171c425cf9addb61ef3f03596fd26355ed8af76d (patch) | |
| tree | e620f9838187ab70fd65b5d6554c3b9252777fd8 /tests/simple | |
| parent | c258b99040c8414952a3aceae874dc47563540dc (diff) | |
| download | yosys-171c425cf9addb61ef3f03596fd26355ed8af76d.tar.gz yosys-171c425cf9addb61ef3f03596fd26355ed8af76d.tar.bz2 yosys-171c425cf9addb61ef3f03596fd26355ed8af76d.zip | |
Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/xfirrtl | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 00e89b389..5bc75347b 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -12,7 +12,6 @@ multiplier.v inst id[0] of muxtree.v drops modules omsp_dbg_uart.v $adff operators.v $pow -paramods.v subfield assignment (bits() <= ...) partsel.v drops modules process.v drops modules realexpr.v drops modules |