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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-31 09:27:38 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-07-31 09:27:38 -0700 |
| commit | 3b8c917025e1be9695468588082e9175e918c9e9 (patch) | |
| tree | 9a744f1ddf3e9ac490341506e1474d6cf05c3b07 /tests/simple | |
| parent | e8341d949f79e501abcf637edd3e7d409e2dd72c (diff) | |
| download | yosys-3b8c917025e1be9695468588082e9175e918c9e9.tar.gz yosys-3b8c917025e1be9695468588082e9175e918c9e9.tar.bz2 yosys-3b8c917025e1be9695468588082e9175e918c9e9.zip | |
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/xfirrtl | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index ba61a4476..10063d2c2 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,10 +1,12 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of +defvalue.sv Initial value not supported dff_different_styles.v dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff +implicit_ports.v not fully initialized macros.v drops modules mem2reg.v drops modules mem_arst.v $adff @@ -12,7 +14,6 @@ memory.v $adff multiplier.v inst id[0] of muxtree.v drops modules omsp_dbg_uart.v $adff -operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules @@ -23,5 +24,6 @@ specify.v no code (empty module generates error subbytes.v $adff task_func.v drops modules values.v combinational loop +wandwor.v Invalid connect to an expression that is not a reference or a WritePort. vloghammer.v combinational loop wreduce.v original verilog issues ( -x where x isn't declared signed) |