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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-31 11:51:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-31 11:51:31 -0700 |
| commit | 3df66027e0de11913aac4b29d6b4ab79550bfb28 (patch) | |
| tree | a6b765abd56b972c4277524c70ee474aec8e4d03 /tests/simple | |
| parent | a0cc795e85541b0326b6d4396a726142f0d0f8bb (diff) | |
| download | yosys-3df66027e0de11913aac4b29d6b4ab79550bfb28.tar.gz yosys-3df66027e0de11913aac4b29d6b4ab79550bfb28.tar.bz2 yosys-3df66027e0de11913aac4b29d6b4ab79550bfb28.zip | |
Add dynamic slicing Verilog testcase
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/dynslice.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v new file mode 100644 index 000000000..7236ac3a5 --- /dev/null +++ b/tests/simple/dynslice.v @@ -0,0 +1,12 @@ +module dynslice ( + input clk , + input [9:0] ctrl , + input [15:0] din , + input [3:0] sel , + output reg [127:0] dout +); +always @(posedge clk) +begin + dout[ctrl*sel+:16] <= din ; +end +endmodule |