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* xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-0/+11
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* ice40_dsp: fix typoEddie Hung2020-01-171-0/+11
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* this one is fineMiodrag Milanovic2020-01-101-3/+3
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* Fix testsMiodrag Milanovic2020-01-103-12/+11
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* Combine tests to check multiple clock domainsEddie Hung2020-01-021-33/+10
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-0/+19
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| * Added a test caseMiodrag Milanovic2020-01-011-0/+19
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* | Add some abc9 dff testsEddie Hung2019-12-311-0/+55
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* | Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3021-54/+189
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| * Merge pull request #1589 from YosysHQ/iopad_defaultMiodrag Milanović2019-12-3019-60/+61
| |\ | | | | | | Make iopad option default for all xilinx flows
| | * Fix new testsMiodrag Milanovic2019-12-283-6/+6
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| | * Merge remote-tracking branch 'origin/master' into iopad_defaultMiodrag Milanovic2019-12-284-0/+118
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| | * | Make test without iopadsMiodrag Milanovic2019-12-2817-51/+51
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| | * | Revert "Fix xilinx tests, when iopads are default"Miodrag Milanovic2019-12-2816-40/+40
| | | | | | | | | | | | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c.
| | * | Addressed review commentsMiodrag Milanovic2019-12-211-1/+0
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| | * | Fix xilinx tests, when iopads are defaultMiodrag Milanovic2019-12-2117-42/+44
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| * | | Add #1598 testcaseEddie Hung2019-12-271-0/+16
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| * | Add DSP cascade testsEddie Hung2019-12-231-0/+89
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| * | xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-223-0/+29
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1911-30/+560
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| * tests/xilinx: fix flaky mux testMarcin Kościelnicki2019-12-181-2/+4
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| * xilinx: Add xilinx_dffopt pass (#1557)Marcin Kościelnicki2019-12-183-3/+232
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| * xilinx: Improve flip-flop handling.Marcin Kościelnicki2019-12-183-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data.
| * Merge pull request #1574 from YosysHQ/eddie/xilinx_lutramEddie Hung2019-12-163-17/+171
| |\ | | | | | | xilinx: add LUTRAM rules for RAM32M, RAM64M
| | * Disable RAM16X1D testEddie Hung2019-12-131-17/+17
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| | * Remove extraneous synth_xilinx callEddie Hung2019-12-121-2/+0
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| | * Add tests for these new modelsEddie Hung2019-12-121-0/+40
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| | * Add #1460 testcaseEddie Hung2019-12-121-0/+34
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| | * Rename memory tests to lutram, add more xilinx testsEddie Hung2019-12-122-17/+99
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| * | Add another testEddie Hung2019-12-161-1/+8
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| * | Accidentally commented out testsEddie Hung2019-12-161-47/+47
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| * | Add unconditional match blocks for force RAMEddie Hung2019-12-161-0/+9
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| * | Merge blockram testsEddie Hung2019-12-162-47/+81
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| * | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-0/+47
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| * | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-131-6/+6
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| * | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-2/+2
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| * | Adding a note (TODO) in the memory_params.ys check fileDiego H2019-12-121-0/+2
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| * | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-121-0/+45
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-1/+1
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| * tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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* | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-0/+91
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* No need for -abc9Eddie Hung2019-11-261-1/+1
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* Add citationEddie Hung2019-11-261-0/+1
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* Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
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* xilinx: Use INV instead of LUT1 when applicableMarcin Kościelnicki2019-11-254-8/+8
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* Fixed testsMiodrag Milanovic2019-11-111-1/+5
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* Common memory test now sharedMiodrag Milanovic2019-10-182-22/+1
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* Share common testsMiodrag Milanovic2019-10-1822-300/+11
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* fix yosys pathMiodrag Milanovic2019-10-181-2/+2
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