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| author | Diego H <diego@symbioticeda.com> | 2019-12-12 17:32:58 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 17:32:58 -0600 |
| commit | 751a18d7e974123352e372c75bb17226e6fabec0 (patch) | |
| tree | 87f644392b8be91788a3af73620a75e93838748c /tests/arch/xilinx | |
| parent | e33f407655fa516cb2f6754103973eb156ca90cf (diff) | |
| download | yosys-751a18d7e974123352e372c75bb17226e6fabec0.tar.gz yosys-751a18d7e974123352e372c75bb17226e6fabec0.tar.bz2 yosys-751a18d7e974123352e372c75bb17226e6fabec0.zip | |
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/memory_params.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index 657629e0f..c1b0ca489 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -37,10 +37,10 @@ cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 select -assert-count 4 t:RAM128X1D -# More than 18K bits and addr <= 36: -> RAMB36E1 +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB36E1 |