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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-21 06:30:06 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-12-18 13:43:43 +0100 |
| commit | aff6ad1ce09264fb7fbf43a7456a746a586bea90 (patch) | |
| tree | bc8edef3141b31acac3c5dad428a8ff50f840cc0 /tests/arch/xilinx | |
| parent | 22dd9f107c8986463041709aabcd0c886c87d33f (diff) | |
| download | yosys-aff6ad1ce09264fb7fbf43a7456a746a586bea90.tar.gz yosys-aff6ad1ce09264fb7fbf43a7456a746a586bea90.tar.bz2 yosys-aff6ad1ce09264fb7fbf43a7456a746a586bea90.zip | |
xilinx: Improve flip-flop handling.
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/adffs.ys | 9 | ||||
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 11 | ||||
| -rw-r--r-- | tests/arch/xilinx/macc.ys | 3 |
3 files changed, 12 insertions, 11 deletions
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index e73bfe0b9..c0ff6a2e2 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -32,10 +32,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivale design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 +select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDSE %% t:* %D design -load read @@ -46,6 +45,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT2 +select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 2a72c34e8..4545cf6d7 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -11,8 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 5 t:FDRE -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT4 -select -assert-count 4 t:LUT6 -select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D +select -assert-count 4 t:FDRE +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT2 +select -assert-count 2 t:LUT3 +select -assert-count 4 t:LUT5 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 6e884b35a..11e959976 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -23,9 +23,10 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc2 # Constrain all select calls below inside the top module + select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 +select -assert-count 40 t:LUT3 select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D |