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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:57:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:57:55 -0800 |
| commit | 378d9e6e0c16e13cf161aec283ab366e2462745c (patch) | |
| tree | eddf33eb6a109295089d8b1859a58106a85e5e09 /tests/arch/xilinx | |
| parent | 4158ce4eda4853e89187824daa32fcb57f6dfa27 (diff) | |
| download | yosys-378d9e6e0c16e13cf161aec283ab366e2462745c.tar.gz yosys-378d9e6e0c16e13cf161aec283ab366e2462745c.tar.bz2 yosys-378d9e6e0c16e13cf161aec283ab366e2462745c.zip | |
Add another test
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/blockram.ys | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 4b7716739..bb908cbbf 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -84,7 +84,14 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory -dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 |