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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:01:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 13:01:51 -0800 |
| commit | e990c013c57da8149dbbd2fe2633e953ec8f471b (patch) | |
| tree | 359aab88fc063ab153fefa41197f62151ae4cfb7 /tests/arch/xilinx | |
| parent | d910bec8e00b5e9eba2fc62dec1a6b734e429cc4 (diff) | |
| download | yosys-e990c013c57da8149dbbd2fe2633e953ec8f471b.tar.gz yosys-e990c013c57da8149dbbd2fe2633e953ec8f471b.tar.bz2 yosys-e990c013c57da8149dbbd2fe2633e953ec8f471b.zip | |
Merge blockram tests
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/blockram.ys | 81 | ||||
| -rw-r--r-- | tests/arch/xilinx/blockram_params.ys | 47 |
2 files changed, 81 insertions, 47 deletions
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys new file mode 100644 index 000000000..362d33229 --- /dev/null +++ b/tests/arch/xilinx/blockram.ys @@ -0,0 +1,81 @@ +### TODO: Not running equivalence checking because BRAM models does not exists +### currently. Checking instance counts instead. +## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +## Anything memory bits < 1024 -> LUTRAM +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 0 t:RAMB18E1 +#select -assert-count 4 t:RAM128X1D +# +## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB36E1 +# +# +#### With parameters + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set logic_block 1 m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys deleted file mode 100644 index 27a94834e..000000000 --- a/tests/arch/xilinx/blockram_params.ys +++ /dev/null @@ -1,47 +0,0 @@ -## TODO: Not running equivalence checking because BRAM models does not exists -## currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -# Anything memory bits < 1024 -> LUTRAM -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM128X1D - -# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 - |