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| author | Diego H <diego@symbioticeda.com> | 2019-12-13 09:33:18 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-13 09:33:18 -0600 |
| commit | 1c9634558747bf5b92a309b6af013a54034c35d3 (patch) | |
| tree | 8bb624eaec5380ba7b1da612dae921a194b292c3 /tests/arch/xilinx | |
| parent | 751a18d7e974123352e372c75bb17226e6fabec0 (diff) | |
| download | yosys-1c9634558747bf5b92a309b6af013a54034c35d3.tar.gz yosys-1c9634558747bf5b92a309b6af013a54034c35d3.tar.bz2 yosys-1c9634558747bf5b92a309b6af013a54034c35d3.zip | |
Renaming BRAM memory tests for the sake of uniformity
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/blockram_params.ys (renamed from tests/arch/xilinx/memory_params.ys) | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/blockram_params.ys index c1b0ca489..27a94834e 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/blockram_params.ys @@ -1,28 +1,28 @@ ## TODO: Not running equivalence checking because BRAM models does not exists ## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp @@ -30,7 +30,7 @@ select -assert-count 1 t:RAMB18E1 # Anything memory bits < 1024 -> LUTRAM design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp @@ -39,7 +39,7 @@ select -assert-count 4 t:RAM128X1D # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp |