Commit message (Collapse) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | ABC9: Cell Port Bug Patch (#3670) | Benjamin Barzen | 2023-04-22 | 2 | -0/+16 |
| | | | | | | | | | | | | | | | | | * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com> | ||||
* | Tests for ram_style = "huge" | KrystalDelusion | 2023-02-21 | 2 | -0/+182 |
| | | | | iCE40 SPRAM and Xilinx URAM | ||||
* | Asymmetric port ram tests with Xilinx | KrystalDelusion | 2023-02-21 | 3 | -0/+193 |
| | | | | Uses verilog code from User Guide 901 (2021.1) | ||||
* | Fix tests for check in equiv_opt | Jannis Harder | 2022-10-07 | 3 | -6/+14 |
| | |||||
* | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 3 | -46/+15 |
| | |||||
* | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 1 | -2/+2 |
| | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 1 | -2/+3 |
| | | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases | ||||
* | ast: Use better parameter serialization for paramod names. | Marcelina Kościelnicka | 2021-03-18 | 1 | -3/+3 |
| | | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme. | ||||
* | xilinx_dffopt: Don't crash on missing IS_*_INVERTED. | Marcelina Kościelnicka | 2021-01-27 | 2 | -1/+48 |
| | | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559. | ||||
* | xilinx: Fix attributes_test.ys | Marcelina Kościelnicka | 2020-10-24 | 1 | -4/+2 |
| | | | | | | | | | | This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory. | ||||
* | Merge pull request #2380 from Xiretza/parallel-tests | clairexen | 2020-10-01 | 1 | -19/+3 |
|\ | | | | | Clean up and parallelize testsuite | ||||
| * | tests: Centralize test collection and Makefile generation | Xiretza | 2020-09-21 | 1 | -19/+3 |
| | | |||||
* | | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325) | Eddie Hung | 2020-09-23 | 1 | -0/+37 |
|/ | | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled | ||||
* | opt_expr: Remove -clkinv option, make it the default. | Marcelina Kościelnicka | 2020-07-31 | 1 | -2/+1 |
| | | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone. | ||||
* | synth_xilinx: Use opt_dff. | Marcelina Kościelnicka | 2020-07-30 | 1 | -9/+7 |
| | | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway. | ||||
* | satgen: Add support for dffe, sdff, sdffe, sdffce cells. | Marcelina Kościelnicka | 2020-07-24 | 1 | -2/+0 |
| | |||||
* | xilinx: Fix srl regression. | Marcelina Kościelnicka | 2020-07-12 | 1 | -0/+41 |
| | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly. | ||||
* | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve | Eddie Hung | 2020-06-04 | 1 | -4/+53 |
|\ | | | | | abc9: -dff improvements | ||||
| * | abc9_ops: update messaging (credit to @Xiretza for spotting) | Eddie Hung | 2020-05-30 | 1 | -4/+4 |
| | | |||||
| * | tests: add test for abc9 -dff removing a redundant flop entirely | Eddie Hung | 2020-05-25 | 1 | -0/+15 |
| | | |||||
| * | tests: add testcase for abc9 -dff preserving flop names | Eddie Hung | 2020-05-25 | 1 | -0/+34 |
| | | |||||
* | | Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings | Eddie Hung | 2020-06-03 | 2 | -2/+2 |
|\ \ | | | | | | | tests: reduce test warnings | ||||
| * | | tests: fix some test warnings | Eddie Hung | 2020-05-25 | 2 | -2/+2 |
| |/ | |||||
* / | tests: xilinx macc test to have initval, shorten BMC depth for runtime | Eddie Hung | 2020-05-25 | 2 | -8/+8 |
|/ | |||||
* | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 1 | -2/+4 |
| | | | | Fixes #2058. | ||||
* | abc9_ops: add -prep_bypass for auto bypass boxes; refactor | Eddie Hung | 2020-05-14 | 1 | -5/+29 |
| | | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier | ||||
* | abc9: suppress warnings when no compatible + used flop boxes formed | Eddie Hung | 2020-05-14 | 1 | -1/+3 |
| | |||||
* | xilinx: update abc9_dff tests | Eddie Hung | 2020-05-14 | 1 | -18/+45 |
| | |||||
* | xilinx: remove no-longer-relevant test | Eddie Hung | 2020-05-14 | 1 | -91/+0 |
| | |||||
* | tests: read +/xilinx/cell_sim.v before xilinx_dsp test | Eddie Hung | 2020-04-22 | 1 | -0/+1 |
| | |||||
* | xilinx: xilinx_dffopt to read cells_sim.v; fix test | Eddie Hung | 2020-04-22 | 1 | -13/+22 |
| | |||||
* | fix argument order for macOS compatibility | N. Engelhardt | 2020-03-18 | 1 | -3/+3 |
| | |||||
* | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" | Eddie Hung | 2020-02-27 | 1 | -3/+9 |
| | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5. | ||||
* | Cleanup tests | Eddie Hung | 2020-02-27 | 1 | -0/+18 |
| | |||||
* | Fix tests/arch/xilinx/fsm.ys to count flops only | Eddie Hung | 2020-02-27 | 1 | -9/+3 |
| | |||||
* | xilinx: Add support for LUT RAM on LUT4-based devices. | Marcin Kościelnicki | 2020-02-07 | 1 | -0/+20 |
| | | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549 | ||||
* | xilinx: Initial support for LUT4 devices. | Marcin Kościelnicki | 2020-02-07 | 3 | -1/+83 |
| | | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547 | ||||
* | abc9_ops: -reintegrate to use derived_type for box_ports | Eddie Hung | 2020-02-05 | 1 | -1/+21 |
| | |||||
* | Add opt_lut_ins pass. (#1673) | Marcelina Kościelnicka | 2020-02-03 | 1 | -0/+25 |
| | |||||
* | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate | N. Engelhardt | 2020-01-28 | 1 | -0/+5 |
|\ | | | | | synth_xilinx: error out if tristate without '-iopad' | ||||
| * | Add test | Eddie Hung | 2019-12-12 | 1 | -0/+5 |
| | | |||||
* | | xilinx_dsp: another typo; move xilinx specific test | Eddie Hung | 2020-01-17 | 1 | -0/+11 |
| | | |||||
* | | ice40_dsp: fix typo | Eddie Hung | 2020-01-17 | 1 | -0/+11 |
| | | |||||
* | | this one is fine | Miodrag Milanovic | 2020-01-10 | 1 | -3/+3 |
| | | |||||
* | | Fix tests | Miodrag Milanovic | 2020-01-10 | 3 | -12/+11 |
| | | |||||
* | | Combine tests to check multiple clock domains | Eddie Hung | 2020-01-02 | 1 | -33/+10 |
| | | |||||
* | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 1 | -0/+19 |
|\ \ | |||||
| * | | Added a test case | Miodrag Milanovic | 2020-01-01 | 1 | -0/+19 |
| | | | |||||
* | | | Add some abc9 dff tests | Eddie Hung | 2019-12-31 | 1 | -0/+55 |
| | | | |||||
* | | | Add -D DFF_MODE to abc9_map test | Eddie Hung | 2019-12-30 | 1 | -4/+4 |
| | | |