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* ABC9: Cell Port Bug Patch (#3670)Benjamin Barzen2023-04-222-0/+16
| | | | | | | | | | | | | | | | | * ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Tests for ram_style = "huge"KrystalDelusion2023-02-212-0/+182
| | | | iCE40 SPRAM and Xilinx URAM
* Asymmetric port ram tests with XilinxKrystalDelusion2023-02-213-0/+193
| | | | Uses verilog code from User Guide 901 (2021.1)
* Fix tests for check in equiv_optJannis Harder2022-10-073-6/+14
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* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-46/+15
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* Fix the tests we just brokeClaire Xenia Wolf2021-12-101-2/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-2/+3
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-3/+3
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* xilinx_dffopt: Don't crash on missing IS_*_INVERTED.Marcelina Kościelnicka2021-01-272-1/+48
| | | | | | | | The presence of IS_*_INVERTED on FD* cells follows Vivado, which apparently has been decided by a dice roll. Just assume false if the parameter doesn't exist. Fixes #2559.
* xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
| | | | | | | | | | This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.
* Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-011-19/+3
|\ | | | | Clean up and parallelize testsuite
| * tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
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* | xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)Eddie Hung2020-09-231-0/+37
|/ | | | | | | | | | | * xilinx: eliminate SCCs from DSP48E1 model * xilinx: add SCC test for DSP48E1 * Update techlibs/xilinx/cells_sim.v * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
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* xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
| | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-4/+53
|\ | | | | abc9: -dff improvements
| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
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| * tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
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| * tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
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* | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-032-2/+2
|\ \ | | | | | | tests: reduce test warnings
| * | tests: fix some test warningsEddie Hung2020-05-252-2/+2
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* / tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
| | | | Fixes #2058.
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
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* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
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* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
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* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
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* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
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* fix argument order for macOS compatibilityN. Engelhardt2020-03-181-3/+3
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* Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
| | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
* Cleanup testsEddie Hung2020-02-271-0/+18
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* Fix tests/arch/xilinx/fsm.ys to count flops onlyEddie Hung2020-02-271-9/+3
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* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-071-0/+20
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-1/+83
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+21
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* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+25
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* Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+5
|\ | | | | synth_xilinx: error out if tristate without '-iopad'
| * Add testEddie Hung2019-12-121-0/+5
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* | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-171-0/+11
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* | ice40_dsp: fix typoEddie Hung2020-01-171-0/+11
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* | this one is fineMiodrag Milanovic2020-01-101-3/+3
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* | Fix testsMiodrag Milanovic2020-01-103-12/+11
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* | Combine tests to check multiple clock domainsEddie Hung2020-01-021-33/+10
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-0/+19
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| * | Added a test caseMiodrag Milanovic2020-01-011-0/+19
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* | | Add some abc9 dff testsEddie Hung2019-12-311-0/+55
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* | | Add -D DFF_MODE to abc9_map testEddie Hung2019-12-301-4/+4
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