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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 16:44:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-27 16:44:57 -0800 |
| commit | d45869855c6fc86dc6a0225018a8e383866dacb4 (patch) | |
| tree | 6e11c22290ad9c5a4200ba44c9e2039c0980886e /tests/arch/xilinx | |
| parent | 237415e78cab2c15d783657c4c2bc959efb298bb (diff) | |
| download | yosys-d45869855c6fc86dc6a0225018a8e383866dacb4.tar.gz yosys-d45869855c6fc86dc6a0225018a8e383866dacb4.tar.bz2 yosys-d45869855c6fc86dc6a0225018a8e383866dacb4.zip | |
Add #1598 testcase
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/bug1598.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys new file mode 100644 index 000000000..1175380b1 --- /dev/null +++ b/tests/arch/xilinx/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module led_blink ( + input clk, + output ledc + ); + + reg [6:0] led_counter = 0; + always @( posedge clk ) begin + led_counter <= led_counter + 1; + end + assign ledc = !led_counter[ 6:3 ]; + +endmodule +EOT +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 |