Share common tests

22 files changed, 11 insertions, 300 deletions

diff --git a/tests/arch/xilinx/add_sub.v b/tests/arch/xilinx/add_sub.v
deleted file mode 100644
index 177c32e30..000000000
--- a/tests/arch/xilinx/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index f06e7fa01..9dbddce47 100644
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
diff --git a/tests/arch/xilinx/adffs.v b/tests/arch/xilinx/adffs.v
deleted file mode 100644
index 223b52d21..000000000
--- a/tests/arch/xilinx/adffs.v
+++ /dev/null
@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index 1923b9802..12c34415e 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/arch/xilinx/counter.v b/tests/arch/xilinx/counter.v
deleted file mode 100644
index 52852f8ac..000000000
--- a/tests/arch/xilinx/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule

diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 459541656..57b645d19 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/xilinx/dffs.v b/tests/arch/xilinx/dffs.v
deleted file mode 100644
index 3418787c9..000000000
--- a/tests/arch/xilinx/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
index f1716dabb..0bba4858f 100644
--- a/tests/arch/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/arch/xilinx/fsm.v b/tests/arch/xilinx/fsm.v
deleted file mode 100644
index 368fbaace..000000000
--- a/tests/arch/xilinx/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

-endmodule

diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index a9e94c2c0..d2b481421 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten
diff --git a/tests/arch/xilinx/latches.v b/tests/arch/xilinx/latches.v
deleted file mode 100644
index adb5d5319..000000000
--- a/tests/arch/xilinx/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index 3eb550a42..fe7887e8d 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp
diff --git a/tests/arch/xilinx/logic.v b/tests/arch/xilinx/logic.v
deleted file mode 100644
index e5343cae0..000000000
--- a/tests/arch/xilinx/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index 9ae5993aa..c0f6da302 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
diff --git a/tests/arch/xilinx/mul.v b/tests/arch/xilinx/mul.v
deleted file mode 100644
index d5b48b1d7..000000000
--- a/tests/arch/xilinx/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
index 66a06efdc..d76814966 100644
--- a/tests/arch/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys
@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
diff --git a/tests/arch/xilinx/mux.v b/tests/arch/xilinx/mux.v
deleted file mode 100644
index 27bc0bf0b..000000000
--- a/tests/arch/xilinx/mux.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 420dece4e..821d0fab7 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2
diff --git a/tests/arch/xilinx/shifter.v b/tests/arch/xilinx/shifter.v
deleted file mode 100644
index 04ae49d83..000000000
--- a/tests/arch/xilinx/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out >> 1;

-		out[7] <= in;

-	end

-

-endmodule

diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys
index 84e16f41e..455437f18 100644
--- a/tests/arch/xilinx/shifter.ys
+++ b/tests/arch/xilinx/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten
diff --git a/tests/arch/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v
deleted file mode 100644
index c64468253..000000000
--- a/tests/arch/xilinx/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output reg o;
-    
-    always @(en or i)
-		o <= (en)? i : 1'bZ;
-endmodule
diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys
index c9cfb8546..4697703ca 100644
--- a/tests/arch/xilinx/tribuf.ys
+++ b/tests/arch/xilinx/tribuf.ys
@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf