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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
| commit | f2576c096cedf0974f237530a9d50e250bf117a3 (patch) | |
| tree | 3f5a0653615a125b0b51a2b135f5ac6d0b95794b /tests/arch/xilinx | |
| parent | b0605128b633f64b07107ba3a673f406e96d42ad (diff) | |
| parent | 9009b76a69b9e867f69295a8e555305925e83aeb (diff) | |
| download | yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.gz yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.bz2 yosys-f2576c096cedf0974f237530a9d50e250bf117a3.zip | |
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'tests/arch/xilinx')
| -rw-r--r-- | tests/arch/xilinx/bug1462.ys | 11 | ||||
| -rw-r--r-- | tests/arch/xilinx/xilinx_dsp.ys | 11 |
2 files changed, 22 insertions, 0 deletions
diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys new file mode 100644 index 000000000..15cab5121 --- /dev/null +++ b/tests/arch/xilinx/bug1462.ys @@ -0,0 +1,11 @@ +read_verilog << EOF +module top(...); +input wire [31:0] A; +output wire [31:0] P; + +assign P = A * 32'h12300000; + +endmodule +EOF + +synth_xilinx diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys new file mode 100644 index 000000000..3b9f52930 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [24:0] a, input [17:0] b, output [42:0] o1, o2, o5); +DSP48E1 m1 (.A(a), .B(16'd1234), .P(o1)); +assign o2 = a * 16'd0; +wire [42:0] o3, o4; +DSP48E1 m2 (.A(a), .B(b), .P(o3)); +assign o4 = a * b; +DSP48E1 m3 (.A(a), .B(b), .P(o5)); +endmodule +EOT +xilinx_dsp |