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Age
Files
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Merge remote-tracking branch 'origin/master' into eddie/cleanup
Eddie Hung
2019-08-07
2
-117
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+252
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Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes
David Shah
2019-08-07
1
-101
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+244
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ecp5: Make cells_sim.v consistent with nextpnr
David Shah
2019-08-07
1
-101
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+244
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Merge pull request #1249 from mmicko/anlogic_fix
Clifford Wolf
2019-08-07
1
-16
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+8
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anlogic : Fix alu mapping
Miodrag Milanovic
2019-08-03
1
-16
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+8
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stoi -> atoi
Eddie Hung
2019-08-07
3
-3
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+3
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Fix spacing
Eddie Hung
2019-08-06
1
-3
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+3
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Use std::stoi instead of atoi(<str>.c_str())
Eddie Hung
2019-08-06
1
-1
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+1
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Make liberal use of IdString.in()
Eddie Hung
2019-08-06
1
-14
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+8
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Clifford Wolf
2019-08-06
1
-0
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+19
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Merge pull request #1239 from mmicko/mingw_fix
Clifford Wolf
2019-08-02
3
-6
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+6
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Fix formatting for msys2 mingw build using GetSize
Miodrag Milanovic
2019-08-01
3
-6
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+6
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RST -> RSTBRST for RAMB8BWER
Eddie Hung
2019-07-29
1
-3
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+3
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Merge branch 'ZirconiumX-synth_intel_m9k'
Clifford Wolf
2019-07-25
4
-5
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+11
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intel: Map M9K BRAM only on families that have it
Dan Ravensloft
2019-07-23
4
-5
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+12
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Merge pull request #1218 from ZirconiumX/synth_intel_iopads
Clifford Wolf
2019-07-25
1
-8
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+8
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intel: Make -noiopads the default
Dan Ravensloft
2019-07-24
1
-8
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+8
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Merge pull request #1224 from YosysHQ/xilinx_fix_ff
Eddie Hung
2019-07-25
1
-2
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+2
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xilinx: Fix missing cell name underscore in cells_map.v
David Shah
2019-07-25
1
-2
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+2
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ice40: Fix test_dsp_model.sh
David Shah
2019-07-19
1
-1
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+1
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ice40/cells_sim.v: Fix sign of J and K partial products
David Shah
2019-07-19
1
-5
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+7
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ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
David Shah
2019-07-19
1
-2
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+2
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Add tests for all combinations of A and B signedness for comb mul
Eddie Hung
2019-07-19
2
-1
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+229
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Don't copy ref if exists already
Eddie Hung
2019-07-19
1
-1
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+3
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Merge pull request #1208 from ZirconiumX/intel_cleanups
David Shah
2019-07-18
1
-29
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+14
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synth_intel: Use stringf
Dan Ravensloft
2019-07-18
1
-7
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+2
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synth_intel: s/not family/no family/
Dan Ravensloft
2019-07-18
1
-2
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+2
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intel_synth: Fix help message
Ben Widawsky
2019-07-18
1
-1
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+1
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intel_synth: Small code cleanup to remove if ladder
Ben Widawsky
2019-07-18
1
-28
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+10
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intel_synth: Make family explicit and match
Ben Widawsky
2019-07-18
1
-2
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+6
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intel_synth: Minor code cleanups
Ben Widawsky
2019-07-18
1
-2
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+6
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synth_intel: rename for consistency with #1184
Dan Ravensloft
2019-07-18
1
-4
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+4
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Merge pull request #1184 from whitequark/synth-better-labels
Clifford Wolf
2019-07-18
5
-17
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+21
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synth_ecp5: rename dram to lutram everywhere.
whitequark
2019-07-16
4
-13
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+13
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synth_{ice40,ecp5}: more sensible pass label naming.
whitequark
2019-07-16
2
-5
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+9
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Merge pull request #1204 from smunaut/fix_1187
David Shah
2019-07-17
2
-4
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+4
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ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
Sylvain Munaut
2019-07-16
2
-4
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+4
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gen_lut to return correctly sized LUT mask
Eddie Hung
2019-07-16
1
-1
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+1
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Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
Eddie Hung
2019-07-16
8
-29
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+120
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$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark
Eddie Hung
2019-07-15
7
-8
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+8
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ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT
Eddie Hung
2019-07-13
1
-9
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+7
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Use Const::from_string() not its constructor...
Eddie Hung
2019-07-12
1
-1
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+1
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Off by one
Eddie Hung
2019-07-12
1
-1
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+1
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Fix spacing
Eddie Hung
2019-07-12
1
-1
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+1
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Remove double push
Eddie Hung
2019-07-12
1
-1
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+0
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Map to and from this box if -abc9
Eddie Hung
2019-07-12
1
-2
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+3
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ice40_opt to handle this box and opt back to SB_LUT4
Eddie Hung
2019-07-12
1
-0
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+48
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Add new box to cells_sim.v
Eddie Hung
2019-07-12
1
-2
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+25
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_ABC macro will map and unmap to this new box
Eddie Hung
2019-07-12
2
-0
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+34
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Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box
Eddie Hung
2019-07-12
3
-25
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+13
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