iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-12/+0
\|
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-8/+0
\|
*	Added "wreduce -memx"	Clifford Wolf	2016-08-20	1	-2/+6
\|
*	Added memory_memx pass, "memory -memx", and "prep -memx"	Clifford Wolf	2016-08-19	1	-2/+17
\|
*	Added greenpak4_dffinv	Clifford Wolf	2016-08-15	3	-0/+199
\|
*	greenpak4: Changed name of inverted output ports for consistency	Andrew Zonenberg	2016-08-14	2	-19/+19
\|
*	greenpak4: Added GP_DFFxI cells	Andrew Zonenberg	2016-08-14	2	-0/+68
\|
*	greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)	Andrew Zonenberg	2016-08-13	1	-10/+10
\|
*	synth_greenpak4: use attrmvcp to move LOC from wires to cells.	whitequark	2016-08-10	1	-0/+2
\|
*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-0/+24
\|
*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	1	-0/+17
\|
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-9/+1
\|
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+16
\|
*	Added GP_DAC cell	Andrew Zonenberg	2016-07-11	1	-0/+8
\|
*	Removed VOUT port of GP_BANDGAP	Andrew Zonenberg	2016-07-11	1	-1/+1
\|
*	Removed splitnets in prep for new gp4par parser	Andrew Zonenberg	2016-07-11	1	-1/+0
\|
*	Added "prep -auto-top" and "synth -auto-top"	Clifford Wolf	2016-07-11	2	-6/+23
\|
*	greenpak4: add GP_COUNT{8,14}_ADV cells.	whitequark	2016-07-10	1	-0/+26
\|
*	Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations	Clifford Wolf	2016-07-08	2	-13/+24
\|
*	Improved ice40_ffinit error reporting	Clifford Wolf	2016-06-30	1	-1/+5
\|
*	Added "deminout"	Clifford Wolf	2016-06-19	1	-0/+1
\|
*	Improved support for $sop cells	Clifford Wolf	2016-06-17	2	-4/+4
\|
*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	1	-0/+28
\|
*	Added "nlutmap -assert"	Clifford Wolf	2016-06-09	1	-3/+3
\|
*	Do not run "wreduce" in "prep -ifx"	Clifford Wolf	2016-06-08	1	-2/+3
\|
*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	1	-2/+11
\|
*	Added GP_DELAY cell	Andrew Zonenberg	2016-05-07	1	-0/+29
\|
*	Fixed typo in port name	Andrew Zonenberg	2016-05-07	1	-1/+1
\|
*	Fixed extra semicolon	Andrew Zonenberg	2016-05-07	1	-1/+1
\|
*	Fixed typo in parameter name	Andrew Zonenberg	2016-05-07	1	-1/+1
\|
*	Added simulation timescale declaration	Andrew Zonenberg	2016-05-07	1	-0/+2
\|
*	Added synth_ice40 support for latches via logic loops	Clifford Wolf	2016-05-06	3	-0/+13
\|
*	Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"	Clifford Wolf	2016-05-06	1	-3/+15
\|
*	Changed order of passes for better handling of INIT attributes on "output ↵	Andrew Zonenberg	2016-05-04	1	-2/+2
\| \| \| \|	reg" FFs
*	Renamed module parameter	Andrew Zonenberg	2016-05-04	1	-4/+4
\|
*	Refactored synth_greenpak4 to use iopadmap for mapping GP_IOBUF/GP_OBUFT ↵	Andrew Zonenberg	2016-05-04	3	-18/+1
\| \| \| \|	cells instead of extract
*	Fixed incorrect signal naming in GP_IOBUF	Andrew Zonenberg	2016-05-04	1	-2/+2
\|
*	Added tri-state I/O extraction for GreenPak	Andrew Zonenberg	2016-05-03	5	-2/+29
\|
*	Added GreenPak I/O buffer cells	Andrew Zonenberg	2016-05-03	1	-0/+17
\|
*	Added comment to clarify GP_ABUF cell	Andrew Zonenberg	2016-05-02	1	-0/+2
\|
*	Added GP_ABUF cell	Andrew Zonenberg	2016-05-02	1	-0/+6
\|
*	Added GP_PGA cell	Andrew Zonenberg	2016-04-27	1	-0/+11
\|
*	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-04-24	2	-64/+80
\|\
\| *	Added "prep -flatten" and "synth -flatten"	Clifford Wolf	2016-04-24	2	-7/+36
\| \|
\| *	Converted "prep" to ScriptPass	Clifford Wolf	2016-04-24	2	-60/+47
\| \|
* \|	Removed VIN_BUF_EN	Andrew Zonenberg	2016-04-24	1	-1/+0
\| \|
* \|	Renamed VOUT to OUT on GP_ACMP cell	Andrew Zonenberg	2016-04-23	1	-1/+3
\| \|
* \|	Added GP_ACMP cell	Andrew Zonenberg	2016-04-23	1	-0/+12
\|/
*	Run clean after splitnets in synth_greenpak4	Clifford Wolf	2016-04-23	1	-1/+1
\|
*	Merge https://github.com/azonenberg/yosys	Clifford Wolf	2016-04-23	1	-1/+7
\|\