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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:14:00 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-05-07 21:14:00 -0700 |
| commit | 85ee88b0ee13eb49bb255d7e66a62fce823c028a (patch) | |
| tree | 96f7914f4bc79fd40adbcf4d2335518485668ad5 /techlibs | |
| parent | a0c19aae55d878576c7481a6a4a5d10ba98c5224 (diff) | |
| download | yosys-85ee88b0ee13eb49bb255d7e66a62fce823c028a.tar.gz yosys-85ee88b0ee13eb49bb255d7e66a62fce823c028a.tar.bz2 yosys-85ee88b0ee13eb49bb255d7e66a62fce823c028a.zip | |
Fixed typo in parameter name
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index da3704638..c4e5a9de1 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -69,7 +69,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT); count <= count - 1'd1; if(count == 0) - count <= COUNT_MAX; + count <= COUNT_TO; /* if((RESET_MODE == "RISING") && RST) |