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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-23 22:53:49 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-23 22:53:49 -0700 |
| commit | 6e215f374dcd92e2c1bff8ad6114f3d3dc9b06f5 (patch) | |
| tree | 47e587134a358c8bf62b6b168a8dc7590fb93619 /techlibs | |
| parent | 512486dcf37f779e6271e299eb186ab2559eb344 (diff) | |
| download | yosys-6e215f374dcd92e2c1bff8ad6114f3d3dc9b06f5.tar.gz yosys-6e215f374dcd92e2c1bff8ad6114f3d3dc9b06f5.tar.bz2 yosys-6e215f374dcd92e2c1bff8ad6114f3d3dc9b06f5.zip | |
Renamed VOUT to OUT on GP_ACMP cell
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index e6b5db750..586b7a9b8 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -13,7 +13,7 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT); assign OUT = INIT[{IN3, IN2, IN1, IN0}]; endmodule -module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg VOUT = 0); +module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT); parameter BANDWIDTH = "HIGH"; parameter VIN_BUF_EN = 0; @@ -21,6 +21,8 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg VOU parameter VIN_ISRC_EN = 0; parameter HYSTERESIS = 0; + initial OUT = 0; + //cannot simulate mixed signal IP endmodule |