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Author
Age
Files
Lines
*
Fix some c++ clang compiler errors
Clifford Wolf
2017-07-03
1
-3
/
+3
*
Apply minor coding style changes to coolrunner2 target
Clifford Wolf
2017-07-03
2
-1
/
+1
*
Merge pull request #352 from rqou/master
Clifford Wolf
2017-07-03
6
-0
/
+645
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*
coolrunner2: Add a few more primitives
Robert Ou
2017-06-25
1
-0
/
+110
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*
coolrunner2: Initial mapping of latches
Robert Ou
2017-06-25
4
-0
/
+63
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*
coolrunner2: Initial mapping of DFFs
Robert Ou
2017-06-25
4
-0
/
+76
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*
coolrunner2: Remove redundant INVERT_PTC
Robert Ou
2017-06-25
2
-4
/
+1
|
*
coolrunner2: Remove debug prints
Robert Ou
2017-06-25
1
-2
/
+0
|
*
coolrunner2: Correctly handle $_NOT_ after $sop
Robert Ou
2017-06-25
1
-5
/
+41
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*
coolrunner2: Also construct the XOR cell in the macrocell
Robert Ou
2017-06-25
2
-7
/
+34
|
*
coolrunner2: Initial techmapping for $sop
Robert Ou
2017-06-25
4
-153
/
+268
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*
coolrunner2: Initial commit
Robert Ou
2017-06-24
3
-0
/
+223
*
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greenpak4_counters: Changed generation of primitive names so that the absorbe...
Andrew Zonenberg
2017-06-24
1
-3
/
+21
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/
*
Add dff2ff.v techmap file
Clifford Wolf
2017-05-31
2
-0
/
+15
*
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
Andrew Zonenberg
2017-05-22
1
-17
/
+70
*
Add $_ANDNOT_ and $_ORNOT_ gates
Clifford Wolf
2017-05-17
1
-0
/
+38
*
Squelch trailing whitespace
Larry Doolittle
2017-04-12
8
-126
/
+126
*
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
dh73
2017-04-05
8
-0
/
+968
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2017-02-25
1
-3
/
+4
|
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*
Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg
2017-02-14
1
-2
/
+0
|
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\
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*
\
Merge https://github.com/cliffordwolf/yosys
Andrew Zonenberg
2017-02-08
1
-0
/
+8
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*
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greenpak4: Added POUT to GP_COUNTx cells
Andrew Zonenberg
2017-01-01
1
-3
/
+4
*
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Add $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf
2017-02-25
1
-0
/
+16
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|
_
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/
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/
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*
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Fix double-call of log_pop() in synth_greenpak4
Clifford Wolf
2017-02-14
1
-2
/
+0
|
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/
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/
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*
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Add $cover cell type and SVA cover() support
Clifford Wolf
2017-02-04
1
-0
/
+8
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/
*
greenpak4: Added INT pin to GP_SPI
Andrew Zonenberg
2016-12-21
1
-1
/
+3
*
greenpak4: removed unused MISO pin from GP_SPI
Andrew Zonenberg
2016-12-21
1
-1
/
+0
*
greenpak4: Removed SPI_BUFFER parameter
Andrew Zonenberg
2016-12-20
1
-1
/
+0
*
greenpak4: replaced MOSI/MISO with single one-way SDAT pin
Andrew Zonenberg
2016-12-20
1
-2
/
+1
*
greenpak4: Changed port names on GP_SPI for clarity
Andrew Zonenberg
2016-12-20
1
-4
/
+4
*
greenpak4: Initial implementation of GP_SPI cell
Andrew Zonenberg
2016-12-20
1
-0
/
+27
*
greenpak4: Updated GP_DCMP cell model
Andrew Zonenberg
2016-12-17
1
-2
/
+20
*
greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.
Andrew Zonenberg
2016-12-16
1
-5
/
+10
*
greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed inte...
Andrew Zonenberg
2016-12-15
1
-5
/
+24
*
greenpak4: More fixups of GP_DCMPx cells
Andrew Zonenberg
2016-12-15
1
-9
/
+3
*
greenpak4: And another typo :(
Andrew Zonenberg
2016-12-15
1
-1
/
+1
*
greenpak4: Fixed another typo
Andrew Zonenberg
2016-12-15
1
-1
/
+1
*
greenpak4: Fixed typo
Andrew Zonenberg
2016-12-15
1
-1
/
+1
*
greenpak4: Cleaned up trailing spaces in cells_sim
Andrew Zonenberg
2016-12-14
1
-60
/
+60
*
greenpak4: Added GP_DCMPREF / GP_DCMPMUX
Andrew Zonenberg
2016-12-14
1
-0
/
+23
*
Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUF
Andrew Zonenberg
2016-12-11
1
-1
/
+9
*
greenpak4: Added support for inferred input/output inverters on latches
Andrew Zonenberg
2016-12-10
1
-4
/
+17
*
greenpak4: Can now techmap inferred D latches (without set/reset or output in...
Andrew Zonenberg
2016-12-10
3
-0
/
+17
*
greenpak4: Inverted D latch cells now have nQ instead of Q as output port nam...
Andrew Zonenberg
2016-12-10
1
-15
/
+15
*
Added GP_DLATCH and GP_DLATCHI
Andrew Zonenberg
2016-12-05
1
-0
/
+18
*
Initial implementation of techlib support for GreenPAK latches. Instantiation...
Andrew Zonenberg
2016-12-05
2
-0
/
+120
*
Updated help text for synth_greenpak4
Andrew Zonenberg
2016-12-05
1
-0
/
+2
*
Indenting fixes in gowin sim cell lib
Clifford Wolf
2016-11-08
1
-20
/
+28
*
Added hex constant support to write_verilog
Clifford Wolf
2016-11-03
1
-1
/
+1
*
iCE40 flow is not experimental anymore
Clifford Wolf
2016-11-01
1
-1
/
+1
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