Squelch trailing whitespace

8 files changed, 126 insertions, 126 deletions

diff --git a/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v b/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
index c32984859..a65d0c991 100644
--- a/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
+++ b/techlibs/altera_intel/cycloneiv/cells_comb_cycloneiv.v
@@ -16,7 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
- 
+
 module VCC (output V);
    assign V = 1'b1;
 endmodule // VCC
@@ -37,23 +37,23 @@ module cycloneiv_io_obuf (output o, input i, input oe);
    assign oe = oe;
 endmodule // fiftyfivenm_io_obuf
 
-/* Altera MAX10 4-input non-fracturable LUT Primitive */ 
+/* Altera MAX10 4-input non-fracturable LUT Primitive */
 module cycloneiv_lcell_comb (output combout, cout,
                              input dataa, datab, datac, datad, cin);
 
 /* Internal parameters which define the behaviour
    of the LUT primitive.
    lut_mask define the lut function, can be expressed in 16-digit bin or hex.
-   sum_lutc_input define the type of LUT (combinational | arithmetic). 
+   sum_lutc_input define the type of LUT (combinational | arithmetic).
    dont_touch for retiming || carry options.
-   lpm_type for WYSIWYG */  
-   
+   lpm_type for WYSIWYG */
+
 parameter lut_mask = 16'hFFFF;
 parameter dont_touch = "off";
 parameter lpm_type = "cycloneiv_lcell_comb";
 parameter sum_lutc_input = "datac";
-  
-reg [1:0] lut_type;  
+
+reg [1:0] lut_type;
 reg cout_rt;
 reg combout_rt;
 wire dataa_w;
@@ -84,7 +84,7 @@ endfunction
 
 initial begin
     if (sum_lutc_input == "datac") lut_type = 0;
-    else 
+    else
     if (sum_lutc_input == "cin")   lut_type = 1;
     else begin
       $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
@@ -94,11 +94,11 @@ end
 
 always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
     if (lut_type == 0) begin // logic function
-        combout_rt = lut_data(lut_mask, dataa_w, datab_w, 
+        combout_rt = lut_data(lut_mask, dataa_w, datab_w,
                             datac_w, datad_w);
     end
     else if (lut_type == 1) begin // arithmetic function
-        combout_rt = lut_data(lut_mask, dataa_w, datab_w, 
+        combout_rt = lut_data(lut_mask, dataa_w, datab_w,
                             cin_w, datad_w);
     end
     cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
@@ -111,17 +111,17 @@ endmodule // cycloneiv_lcell_comb
 
 /* Altera Cyclone IV Flip-Flop Primitive */
 // TODO: Implement advanced simulation functions
-module dffeas ( output q, 
-                input d, clk, clrn, prn, ena, 
+module dffeas ( output q,
+                input d, clk, clrn, prn, ena,
 		input asdata, aload, sclr, sload );
-  								     
+
 parameter power_up="dontcare";
 parameter is_wysiwyg="false";
   reg q;
 
   always @(posedge clk)
     q <= d;
-   
+
 endmodule
 
 
diff --git a/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v b/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
index 9860647ae..e02332712 100644
--- a/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
+++ b/techlibs/altera_intel/cycloneiv/cells_map_cycloneiv.v
@@ -16,7 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
- 
+
 // Flip-flop D
 module  \$_DFF_P_ (input D, input C, output Q);
    parameter WYSIWYG="TRUE";
@@ -26,12 +26,12 @@ endmodule //
 // Input buffer map
 module \$__inpad (input I, output O);
     cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule 
+endmodule
 
-// Output buffer map   
+// Output buffer map
 module \$__outpad (input I, output O);
     cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule 
+endmodule
 
 // LUT Map
 /* 0 -> datac
@@ -41,14 +41,14 @@ module \$lut (A, Y);
    parameter LUT    = 0;
    input [WIDTH-1:0] A;
    output 	     Y;
-   generate 
+   generate
       if (WIDTH == 1) begin
 	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
       end else
       if (WIDTH == 2) begin
            cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
       end else
-      if(WIDTH == 3) begin 
+      if(WIDTH == 3) begin
 	   cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
       end else
       if(WIDTH == 4) begin
@@ -58,4 +58,4 @@ module \$lut (A, Y);
    endgenerate
 endmodule //
 
-	    
+
diff --git a/techlibs/altera_intel/lpm_functions.v b/techlibs/altera_intel/lpm_functions.v
index 20dbf4a02..b4d02dcb9 100644
--- a/techlibs/altera_intel/lpm_functions.v
+++ b/techlibs/altera_intel/lpm_functions.v
@@ -16,48 +16,48 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
- 
+
 // NOTE: This is still WIP.
 (* techmap_celltype = "$altpll" *)
-module _80_altpll_altera  ( input [1:0] inclk, 
-			    input       fbin, 
-			    input       pllena, 
-			    input       clkswitch, 
-			    input       areset, 
-			    input       pfdena, 
-			    input       clkena, 
-			    input       extclkena, 
-			    input       scanclk, 
-			    input 	scanaclr, 
-			    input       scanclkena, 
-			    input       scanread, 
-			    input       scanwrite, 
-			    input       scandata, 
-			    input       phasecounterselect, 
+module _80_altpll_altera  ( input [1:0] inclk,
+			    input       fbin,
+			    input       pllena,
+			    input       clkswitch,
+			    input       areset,
+			    input       pfdena,
+			    input       clkena,
+			    input       extclkena,
+			    input       scanclk,
+			    input 	scanaclr,
+			    input       scanclkena,
+			    input       scanread,
+			    input       scanwrite,
+			    input       scandata,
+			    input       phasecounterselect,
 			    input       phaseupdown,
 			    input       phasestep,
 			    input       configupdate,
 			    inout       fbmimicbidir,
-			    
-			    output [width_clock-1:0] clk, 
-			    output [3:0]             extclk,     
-			    output [1:0]             clkbad,     
-			    output 	             enable0,     
-			    output 		     enable1,     
-			    output 		     activeclock, 
-			    output 		     clkloss,     
-			    output 		     locked,      
-			    output 		     scandataout, 
-			    output 		     scandone,    
-			    output 		     sclkout0,    
-			    output 		     sclkout1,    
+
+			    output [width_clock-1:0] clk,
+			    output [3:0]             extclk,
+			    output [1:0]             clkbad,
+			    output 	             enable0,
+			    output 		     enable1,
+			    output 		     activeclock,
+			    output 		     clkloss,
+			    output 		     locked,
+			    output 		     scandataout,
+			    output 		     scandone,
+			    output 		     sclkout0,
+			    output 		     sclkout1,
 			    output 	             phasedone,
 			    output 		     vcooverrange,
 			    output 		     vcounderrange,
 			    output 		     fbout,
 			    output 		     fref,
 			    output 		     icdrclk );
-			    
+
 			    parameter   intended_device_family    = "MAX 10";
 			    parameter   operation_mode            = "NORMAL";
 			    parameter   pll_type                  = "AUTO";
@@ -123,7 +123,7 @@ module _80_altpll_altera  ( input [1:0] inclk,
 			    parameter   clk2_phase_shift        = "0";
 			    parameter   clk1_phase_shift        = "0";
 			    parameter   clk0_phase_shift        = "0";
-			    
+
 			    parameter   clk9_duty_cycle         = 50;
 			    parameter   clk8_duty_cycle         = 50;
 			    parameter   clk7_duty_cycle         = 50;
@@ -166,7 +166,7 @@ module _80_altpll_altera  ( input [1:0] inclk,
 			    parameter   pfd_min             = 0;
 			    parameter   pfd_max             = 0;
 			    parameter   m_initial           = 1;
-			    parameter   m                   = 0; 
+			    parameter   m                   = 0;
 			    parameter   n                   = 1;
 			    parameter   m2                  = 1;
 			    parameter   n2                  = 1;
@@ -316,4 +316,4 @@ module _80_altpll_altera  ( input [1:0] inclk,
 			    parameter port_scanclkena = "PORT_CONNECTIVITY";
 			    parameter using_fbmimicbidir_port = "ON";
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/techlibs/altera_intel/max10/cells_arith_max10.v b/techlibs/altera_intel/max10/cells_arith_max10.v
index 497f44d99..82572fb5d 100644
--- a/techlibs/altera_intel/max10/cells_arith_max10.v
+++ b/techlibs/altera_intel/max10/cells_arith_max10.v
@@ -26,7 +26,7 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
    parameter B_WIDTH  = 1;
    parameter Y_WIDTH  = 1;
    parameter LUT      = 0;
-   
+
    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] X, Y;
@@ -44,19 +44,19 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
    wire [Y_WIDTH-1:0] AA = A_buf;
    wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
    wire [Y_WIDTH-1:0] C = {CO, CI};
-   
+
    genvar i;
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
-	   fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("cin")) _TECHMAP_REPLACE_ 
-	                                                                             ( .dataa(AA), 
-										       .datab(BB), 
-										       .datac(C), 
-										       .datad(1'b0), 
-										       .cin(C[i]), 
+	   fiftyfivenm_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("cin")) _TECHMAP_REPLACE_
+	                                                                             ( .dataa(AA),
+										       .datab(BB),
+										       .datac(C),
+										       .datad(1'b0),
+										       .cin(C[i]),
 										       .cout(CO[i]),
 										       .combout(Y[i]) );
 	  end: slice
 	endgenerate
   assign X = C;
 endmodule
-   
+
diff --git a/techlibs/altera_intel/max10/cells_comb_max10.v b/techlibs/altera_intel/max10/cells_comb_max10.v
index cbf0954aa..51adb72e2 100644
--- a/techlibs/altera_intel/max10/cells_comb_max10.v
+++ b/techlibs/altera_intel/max10/cells_comb_max10.v
@@ -16,7 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
- 
+
 module VCC (output V);
    assign V = 1'b1;
 endmodule // VCC
@@ -25,7 +25,7 @@ module GND (output G);
    assign G = 1'b0;
 endmodule // GND
 
-/* Altera MAX10 devices Input Buffer Primitive */ 
+/* Altera MAX10 devices Input Buffer Primitive */
 module fiftyfivenm_io_ibuf (output o, input i, input ibar);
    assign ibar = ibar;
    assign o    = i;
@@ -37,23 +37,23 @@ module fiftyfivenm_io_obuf (output o, input i, input oe);
    assign oe = oe;
 endmodule // fiftyfivenm_io_obuf
 
-/* Altera MAX10 4-input non-fracturable LUT Primitive */ 
+/* Altera MAX10 4-input non-fracturable LUT Primitive */
 module fiftyfivenm_lcell_comb (output combout, cout,
                                input  dataa, datab, datac, datad, cin);
-                               
+
 /* Internal parameters which define the behaviour
    of the LUT primitive.
    lut_mask define the lut function, can be expressed in 16-digit bin or hex.
-   sum_lutc_input define the type of LUT (combinational | arithmetic). 
+   sum_lutc_input define the type of LUT (combinational | arithmetic).
    dont_touch for retiming || carry options.
-   lpm_type for WYSIWYG */   
-   
+   lpm_type for WYSIWYG */
+
 parameter lut_mask = 16'hFFFF;
 parameter dont_touch = "off";
 parameter lpm_type = "fiftyfivenm_lcell_comb";
 parameter sum_lutc_input = "datac";
-  
-reg [1:0] lut_type;  
+
+reg [1:0] lut_type;
 reg cout_rt;
 reg combout_rt;
 wire dataa_w;
@@ -84,7 +84,7 @@ endfunction
 
 initial begin
     if (sum_lutc_input == "datac") lut_type = 0;
-    else 
+    else
     if (sum_lutc_input == "cin")   lut_type = 1;
     else begin
       $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input);
@@ -94,11 +94,11 @@ end
 
 always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
     if (lut_type == 0) begin // logic function
-        combout_rt = lut_data(lut_mask, dataa_w, datab_w, 
+        combout_rt = lut_data(lut_mask, dataa_w, datab_w,
                             datac_w, datad_w);
     end
     else if (lut_type == 1) begin // arithmetic function
-        combout_rt = lut_data(lut_mask, dataa_w, datab_w, 
+        combout_rt = lut_data(lut_mask, dataa_w, datab_w,
                             cin_w, datad_w);
     end
     cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0);
@@ -111,17 +111,17 @@ endmodule // fiftyfivenm_lcell_comb
 
 /* Altera MAX10 D Flip-Flop Primitive */
 // TODO: Implement advanced simulation functions
-module dffeas ( output q, 
-                input d, clk, clrn, prn, ena, 
+module dffeas ( output q,
+                input d, clk, clrn, prn, ena,
 		input asdata, aload, sclr, sload );
-  								     
+
 parameter power_up="dontcare";
 parameter is_wysiwyg="false";
   reg q;
 
   always @(posedge clk)
     q <= d;
-   
+
 endmodule
 
 
diff --git a/techlibs/altera_intel/max10/cells_map_max10.v b/techlibs/altera_intel/max10/cells_map_max10.v
index 9ae6871fa..ed63c521b 100644
--- a/techlibs/altera_intel/max10/cells_map_max10.v
+++ b/techlibs/altera_intel/max10/cells_map_max10.v
@@ -16,7 +16,7 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
- 
+
 // Flip-flop D
 module  \$_DFF_P_ (input D, input C, output Q);
    parameter WYSIWYG="TRUE";
@@ -26,12 +26,12 @@ endmodule //
 // Input buffer map
 module \$__inpad (input I, output O);
     fiftyfivenm_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule 
+endmodule
 
-// Output buffer map   
+// Output buffer map
 module \$__outpad (input I, output O);
     fiftyfivenm_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule 
+endmodule
 
 // LUT Map
 /* 0 -> datac
@@ -41,14 +41,14 @@ module \$lut (A, Y);
    parameter LUT    = 0;
    input [WIDTH-1:0] A;
    output 	     Y;
-   generate 
+   generate
       if (WIDTH == 1) begin
 	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
       end else
       if (WIDTH == 2) begin
            fiftyfivenm_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
       end else
-      if(WIDTH == 3) begin 
+      if(WIDTH == 3) begin
 	   fiftyfivenm_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
       end else
       if(WIDTH == 4) begin
@@ -58,4 +58,4 @@ module \$lut (A, Y);
    endgenerate
 endmodule //
 
-	    
+
diff --git a/techlibs/altera_intel/synth_intel.cc b/techlibs/altera_intel/synth_intel.cc
index 9710f7a85..003059458 100644
--- a/techlibs/altera_intel/synth_intel.cc
+++ b/techlibs/altera_intel/synth_intel.cc
@@ -110,7 +110,7 @@ struct SynthIntelPass : public ScriptPass {
 
 		if (!design->full_selection())
 			log_cmd_error("This comannd only operates on fully selected designs!\n");
-		
+
                 if (family_opt != "max10" && family_opt !="cycloneiv" )
 		  log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 
diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc
index 998bb73bd..a606fd8af 100644
--- a/techlibs/greenpak4/greenpak4_counters.cc
+++ b/techlibs/greenpak4/greenpak4_counters.cc
@@ -66,11 +66,11 @@ bool is_full_bus(
 			else if(!other_conns_allowed)
 				return false;
 		}
-		
+
 		if( (!found_a) || (!found_b) )
 			return false;
 	}
-	
+
 	return true;
 }
 
@@ -83,7 +83,7 @@ bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
 		if(ports.size() > 1)
 			return false;
 	}
-	
+
 	return true;
 }
 
@@ -105,18 +105,18 @@ struct CounterExtraction
 int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract)
 {
 	SigMap& sigmap = index.sigmap;
-	
+
 	//GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
 	int a_width = cell->getParam("\\A_WIDTH").as_int();
 	extract.width = a_width;
 	if(a_width > 14)
 		return 1;
-		
+
 	//Second input must be a single bit
 	int b_width = cell->getParam("\\B_WIDTH").as_int();
 	if(b_width != 1)
 		return 2;
-		
+
 	//Both inputs must be unsigned, so don't extract anything with a signed input
 	bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
 	bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
@@ -128,7 +128,7 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 	const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
 	if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
 		return 4;
-		
+
 	//BI and CI must be constant 1 as well
 	const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
 	if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
@@ -136,13 +136,13 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 	const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
 	if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
 		return 6;
-				
+
 	//CO and X must be unconnected (exactly one connection to each port)
 	if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
 		return 7;
 	if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
 		return 8;
-		
+
 	//Y must have exactly one connection, and it has to be a $mux cell.
 	//We must have a direct bus connection from our Y to their A.
 	const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
@@ -161,26 +161,26 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 	if(!underflow.is_fully_const())
 		return 12;
 	extract.count_value = underflow.as_int();
-	
+
 	//S connection of the mux must come from an inverter (need not be the only load)
 	const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
 	extract.outsig = muxsel;
 	pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
 	Cell* underflow_inv = NULL;
 	for(auto c : muxsel_conns)
-	{		
+	{
 		if(c->type != "$logic_not")
 			continue;
 		if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
 			continue;
-	
+
 		underflow_inv = c;
 		break;
 	}
 	if(underflow_inv == NULL)
 		return 13;
 	extract.underflow_inv = underflow_inv;
-	
+
 	//Y connection of the mux must have exactly one load, the counter's internal register
 	const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
 	pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
@@ -193,14 +193,14 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 	else if(count_reg->type == "$adff")
 	{
 		extract.has_reset = true;
-		
+
 		//Verify ARST_VALUE is zero and ARST_POLARITY is 1
 		//TODO: infer an inverter to make it 1 if necessary, so we can support negative level resets?
 		if(count_reg->getParam("\\ARST_POLARITY").as_int() != 1)
 			return 22;
 		if(count_reg->getParam("\\ARST_VALUE").as_int() != 0)
 			return 23;
-			
+
 		//Save the reset
 		extract.rst = sigmap(count_reg->getPort("\\ARST"));
 	}
@@ -209,9 +209,9 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 		return 15;
 	if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
 		return 16;
-		
+
 	//TODO: Verify count_reg CLK_POLARITY is 1
-		
+
 	//Register output must have exactly two loads, the inverter and ALU
 	const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q"));
 	pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
@@ -221,10 +221,10 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 		return 18;
 	if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
 		return 19;
-		
+
 	//Look up the clock from the register
 	extract.clk = sigmap(count_reg->getPort("\\CLK"));
-	
+
 	//Register output net must have an INIT attribute equal to the count value
 	extract.rwire = cnout.as_wire();
 	if(extract.rwire->attributes.find("\\init") == extract.rwire->attributes.end())
@@ -232,7 +232,7 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction
 	int rinit = extract.rwire->attributes["\\init"].as_int();
 	if(rinit != extract.count_value)
 		return 21;
-		
+
 	return 0;
 }
 
@@ -243,11 +243,11 @@ void greenpak4_counters_worker(
 	pool<Cell*>& cells_to_remove)
 {
 	SigMap& sigmap = index.sigmap;
-	
+
 	//Core of the counter must be an ALU
 	if (cell->type != "$alu")
 		return;
-	
+
 	//A input is the count value. Check if it has COUNT_EXTRACT set.
 	//If it's not a wire, don't even try
 	auto port = sigmap(cell->getPort("\\A"));
@@ -268,7 +268,7 @@ void greenpak4_counters_worker(
 				log_id(a_wire),
 				count_reg_src.c_str(),
 				extract_value.c_str());
-				
+
 			if(extract_value == "FORCE")
 				force_extract = true;
 			else if(extract_value == "NO")
@@ -280,15 +280,15 @@ void greenpak4_counters_worker(
 					extract_value.c_str());
 		}
 	}
-	
+
 	//If we're explicitly told not to extract, don't infer a counter
 	if(never_extract)
 		return;
-	
+
 	//Attempt to extract a counter
 	CounterExtraction extract;
 	int reason = greenpak4_counters_tryextract(index, cell, extract);
-	
+
 	//Nonzero code - we could not find a matchable counter.
 	//Do nothing, unless extraction was forced in which case give an error
 	if(reason != 0)
@@ -320,7 +320,7 @@ void greenpak4_counters_worker(
 			"Reset polarity is not positive",				//22
 			"Reset is not to zero"							//23
 		};
-		
+
 		if(force_extract)
 		{
 			log_error(
@@ -330,12 +330,12 @@ void greenpak4_counters_worker(
 		}
 		return;
 	}
-	
+
 	//Figure out the final cell type based on the counter size
 	string celltype = "\\GP_COUNT8";
 	if(extract.width > 8)
 		celltype = "\\GP_COUNT14";
-	
+
 	//Log it
 	total_counters ++;
 	string reset_type = "non-resettable";
@@ -350,7 +350,7 @@ void greenpak4_counters_worker(
 		extract.count_value,
 		log_id(extract.rwire->name),
 		count_reg_src.c_str());
-	
+
 	//Wipe all of the old connections to the ALU
 	cell->unsetPort("\\A");
 	cell->unsetPort("\\B");
@@ -367,7 +367,7 @@ void greenpak4_counters_worker(
 
 	//Change the cell type
 	cell->type = celltype;
-	
+
 	//Hook up resets
 	if(extract.has_reset)
 	{
@@ -380,14 +380,14 @@ void greenpak4_counters_worker(
 		cell->setParam("\\RESET_MODE", RTLIL::Const("RISING"));
 		cell->setPort("\\RST", RTLIL::SigSpec(false));
 	}
-	
+
 	//Hook up other stuff
 	cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
 	cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value));
-	
+
 	cell->setPort("\\CLK", extract.clk);
 	cell->setPort("\\OUT", extract.outsig);
-	
+
 	//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
 	cells_to_remove.insert(extract.count_mux);
 	cells_to_remove.insert(extract.count_reg);
@@ -409,7 +409,7 @@ struct Greenpak4CountersPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		log_header(design, "Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
-		
+
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -419,21 +419,21 @@ struct Greenpak4CountersPass : public Pass {
 			break;
 		}
 		extra_args(args, argidx, design);
-		
+
 		//Extract all of the counters we could find
 		unsigned int total_counters = 0;
 		for (auto module : design->selected_modules())
 		{
 			pool<Cell*> cells_to_remove;
-			
+
 			ModIndex index(module);
 			for (auto cell : module->selected_cells())
 				greenpak4_counters_worker(index, cell, total_counters, cells_to_remove);
-				
+
 			for(auto cell : cells_to_remove)
 				module->remove(cell);
 		}
-		
+
 		if(total_counters)
 			log("Extracted %u counters\n", total_counters);
 	}